IEICE TRANSACTIONS on Fundamentals
Modeling the Influence of Input-to-Output Coupling Capacitance on CMOS Inverter Delay
Summary :
The modeling of gate delays has always been one of the most difficult and market-sensitive works. In submicron designs, the second-order effects such as the input-to-output coupling capacitance have a significant influence on gate delay as shown in this paper. However, the accurate analysis of the input-to-output coupling capacitance effect has not been presented in previous research. In this paper, an analytical model for the influence of the input-to-output coupling capacitance on CMOS inverter delay is proposed, in which a novel algorithm for computing overshooting time is given. Experimental results show good agreement with Spice simulations.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E89-A No.4 pp.840-846
- Publication Date
- 2006/04/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1093/ietfec/e89-a.4.840
- Type of Manuscript
- Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- Category
Authors
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Zhangcai HUANG, Atsushi KUROKAWA, Yun YANG, Hong YU, Yasuaki INOUE, "Modeling the Influence of Input-to-Output Coupling Capacitance on CMOS Inverter Delay" in IEICE TRANSACTIONS on Fundamentals,
vol. E89-A, no. 4, pp. 840-846, April 2006, doi: 10.1093/ietfec/e89-a.4.840.
Abstract: The modeling of gate delays has always been one of the most difficult and market-sensitive works. In submicron designs, the second-order effects such as the input-to-output coupling capacitance have a significant influence on gate delay as shown in this paper. However, the accurate analysis of the input-to-output coupling capacitance effect has not been presented in previous research. In this paper, an analytical model for the influence of the input-to-output coupling capacitance on CMOS inverter delay is proposed, in which a novel algorithm for computing overshooting time is given. Experimental results show good agreement with Spice simulations.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e89-a.4.840/_p
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@ARTICLE{e89-a_4_840,
author={Zhangcai HUANG, Atsushi KUROKAWA, Yun YANG, Hong YU, Yasuaki INOUE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Modeling the Influence of Input-to-Output Coupling Capacitance on CMOS Inverter Delay},
year={2006},
volume={E89-A},
number={4},
pages={840-846},
abstract={The modeling of gate delays has always been one of the most difficult and market-sensitive works. In submicron designs, the second-order effects such as the input-to-output coupling capacitance have a significant influence on gate delay as shown in this paper. However, the accurate analysis of the input-to-output coupling capacitance effect has not been presented in previous research. In this paper, an analytical model for the influence of the input-to-output coupling capacitance on CMOS inverter delay is proposed, in which a novel algorithm for computing overshooting time is given. Experimental results show good agreement with Spice simulations.},
keywords={},
doi={10.1093/ietfec/e89-a.4.840},
ISSN={1745-1337},
month={April},}
Copy
TY - JOUR
TI - Modeling the Influence of Input-to-Output Coupling Capacitance on CMOS Inverter Delay
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 840
EP - 846
AU - Zhangcai HUANG
AU - Atsushi KUROKAWA
AU - Yun YANG
AU - Hong YU
AU - Yasuaki INOUE
PY - 2006
DO - 10.1093/ietfec/e89-a.4.840
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E89-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2006
AB - The modeling of gate delays has always been one of the most difficult and market-sensitive works. In submicron designs, the second-order effects such as the input-to-output coupling capacitance have a significant influence on gate delay as shown in this paper. However, the accurate analysis of the input-to-output coupling capacitance effect has not been presented in previous research. In this paper, an analytical model for the influence of the input-to-output coupling capacitance on CMOS inverter delay is proposed, in which a novel algorithm for computing overshooting time is given. Experimental results show good agreement with Spice simulations.
ER -
English
