IEICE TRANSACTIONS on Electronics
Low Power CMOS Design Challenges
Summary :
Technology scaling will become difficult due to power wall. On the other hand, future computer and communications technology will require further reduction in power dissipation. Since no new energy efficient device technology is on the horizon, low power CMOS design should be challenged. This paper discusses what and how much designers can do for CMOS power reduction.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E84-C No.8 pp.1021-1028
- Publication Date
- 2001/08/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section INVITED PAPER (Special Issue on Silicon Nanodevices)
- Category
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Tadahiro KURODA, "Low Power CMOS Design Challenges" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 8, pp. 1021-1028, August 2001, doi: .
Abstract: Technology scaling will become difficult due to power wall. On the other hand, future computer and communications technology will require further reduction in power dissipation. Since no new energy efficient device technology is on the horizon, low power CMOS design should be challenged. This paper discusses what and how much designers can do for CMOS power reduction.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_8_1021/_p
Copy
@ARTICLE{e84-c_8_1021,
author={Tadahiro KURODA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Low Power CMOS Design Challenges},
year={2001},
volume={E84-C},
number={8},
pages={1021-1028},
abstract={Technology scaling will become difficult due to power wall. On the other hand, future computer and communications technology will require further reduction in power dissipation. Since no new energy efficient device technology is on the horizon, low power CMOS design should be challenged. This paper discusses what and how much designers can do for CMOS power reduction.},
keywords={},
doi={},
ISSN={},
month={August},}
Copy
TY - JOUR
TI - Low Power CMOS Design Challenges
T2 - IEICE TRANSACTIONS on Electronics
SP - 1021
EP - 1028
AU - Tadahiro KURODA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2001
AB - Technology scaling will become difficult due to power wall. On the other hand, future computer and communications technology will require further reduction in power dissipation. Since no new energy efficient device technology is on the horizon, low power CMOS design should be challenged. This paper discusses what and how much designers can do for CMOS power reduction.
ER -
English
