Technology scaling will become difficult due to power wall. On the other hand, future computer and communications technology will require further reduction in power dissipation. Since no new energy efficient device technology is on the horizon, low power CMOS design should be challenged. This paper discusses what and how much designers can do for CMOS power reduction.

This paper describes a Variable Threshold-voltage CMOS technology (VTCMOS) which controls the threshold voltage (VTH) by means of substrate bias control. Circuit techniques to combine a switch circuit for an active mode and a pump circuit for a standby mode are presented. Design considerations, such as latch-up immunity and upper limit of reverse substrate bias, are discussed. Experimental results obtained from chips fabricated in a 0.3 µm VTCMOS technology are reported. VTH controllability including temperature dependence and influence on short channel effect, power penalty caused by the control circuit, substrate current dependence at low VTH, and substrate noise influence on circuit performance are investigated. A scaling theory is also presented for use in the discussion of future possibilities and problems involved in this technology.