IEICE TRANSACTIONS on Electronics
Variable Threshold-Voltage CMOS Technology
Summary :
This paper describes a Variable Threshold-voltage CMOS technology (VTCMOS) which controls the threshold voltage (VTH) by means of substrate bias control. Circuit techniques to combine a switch circuit for an active mode and a pump circuit for a standby mode are presented. Design considerations, such as latch-up immunity and upper limit of reverse substrate bias, are discussed. Experimental results obtained from chips fabricated in a 0.3 µm VTCMOS technology are reported. VTH controllability including temperature dependence and influence on short channel effect, power penalty caused by the control circuit, substrate current dependence at low VTH, and substrate noise influence on circuit performance are investigated. A scaling theory is also presented for use in the discussion of future possibilities and problems involved in this technology.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E83-C No.11 pp.1705-1715
- Publication Date
- 2000/11/25
- Publicized
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- Type of Manuscript
- Special Section INVITED PAPER (Special Issue on Low-power LSIs and Technologies)
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Tadahiro KURODA, Tetsuya FUJITA, Fumitoshi HATORI, Takayasu SAKURAI, "Variable Threshold-Voltage CMOS Technology" in IEICE TRANSACTIONS on Electronics,
vol. E83-C, no. 11, pp. 1705-1715, November 2000, doi: .
Abstract: This paper describes a Variable Threshold-voltage CMOS technology (VTCMOS) which controls the threshold voltage (VTH) by means of substrate bias control. Circuit techniques to combine a switch circuit for an active mode and a pump circuit for a standby mode are presented. Design considerations, such as latch-up immunity and upper limit of reverse substrate bias, are discussed. Experimental results obtained from chips fabricated in a 0.3 µm VTCMOS technology are reported. VTH controllability including temperature dependence and influence on short channel effect, power penalty caused by the control circuit, substrate current dependence at low VTH, and substrate noise influence on circuit performance are investigated. A scaling theory is also presented for use in the discussion of future possibilities and problems involved in this technology.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e83-c_11_1705/_p
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@ARTICLE{e83-c_11_1705,
author={Tadahiro KURODA, Tetsuya FUJITA, Fumitoshi HATORI, Takayasu SAKURAI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Variable Threshold-Voltage CMOS Technology},
year={2000},
volume={E83-C},
number={11},
pages={1705-1715},
abstract={This paper describes a Variable Threshold-voltage CMOS technology (VTCMOS) which controls the threshold voltage (VTH) by means of substrate bias control. Circuit techniques to combine a switch circuit for an active mode and a pump circuit for a standby mode are presented. Design considerations, such as latch-up immunity and upper limit of reverse substrate bias, are discussed. Experimental results obtained from chips fabricated in a 0.3 µm VTCMOS technology are reported. VTH controllability including temperature dependence and influence on short channel effect, power penalty caused by the control circuit, substrate current dependence at low VTH, and substrate noise influence on circuit performance are investigated. A scaling theory is also presented for use in the discussion of future possibilities and problems involved in this technology.},
keywords={},
doi={},
ISSN={},
month={November},}
Copy
TY - JOUR
TI - Variable Threshold-Voltage CMOS Technology
T2 - IEICE TRANSACTIONS on Electronics
SP - 1705
EP - 1715
AU - Tadahiro KURODA
AU - Tetsuya FUJITA
AU - Fumitoshi HATORI
AU - Takayasu SAKURAI
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E83-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2000
AB - This paper describes a Variable Threshold-voltage CMOS technology (VTCMOS) which controls the threshold voltage (VTH) by means of substrate bias control. Circuit techniques to combine a switch circuit for an active mode and a pump circuit for a standby mode are presented. Design considerations, such as latch-up immunity and upper limit of reverse substrate bias, are discussed. Experimental results obtained from chips fabricated in a 0.3 µm VTCMOS technology are reported. VTH controllability including temperature dependence and influence on short channel effect, power penalty caused by the control circuit, substrate current dependence at low VTH, and substrate noise influence on circuit performance are investigated. A scaling theory is also presented for use in the discussion of future possibilities and problems involved in this technology.
ER -
English
