1-1hit |
Chih-Chun TANG Chia-Hsin WU Wu-Sheng FENG Shen-Iuan LIU
In this paper, a CMOS down-conversion double-balanced mixer is presented with the modified low voltage design technique. The frequencies of the radio frequency (RF) signal, local oscillator (LO) and intermediate frequency (IF) are 2.4 GHz, 2.3 GHz and 100 MHz, respectively. Measurement results of the proposed mixer exhibit 6.7 dB of conversion gain, -18 dBm of input 1 dB compression point (P-1 dB), -8 dBm of input-referred third-order intercept point (IIP3), and 14.7 dB single-side band (SSB) noise figure (NF) while applying -8 dBm LO power and consumes 3.3 mA from 1.8 V supply voltage. It can provide 0.7 dB conversion gain when the supply voltage reduces to 1.3 V. This mixer was fabricated in a 0.35 µm 1P4M standard digital CMOS process and the die size is 1.5 1.1 mm2.