Symmetric Mach-Zehnder (SMZ) type all-optical swit-ches are discussed. The SMZ type all-optical switches feature the so-called differential phase modulation scheme to achieve a speed unrestricted by efficient, thus usually slow nonlinearities. In these switches, semiconductor optical amplifiers (SOAs) are often used to realize low optical power switching. We discussed SOAs from a view point of all-optical switch applications, rather than amplifier applications. Finally, all-optical signal processing experiments are discussed with the SMZ type all-optical switches. These include ultrafast demultiplexing of 336 Gb/s signal pulses and random operations at 42 Gb/s for all-optical logic operation and wavelength conversion.

Control scheme for accurately optimizing (and also automatically stabilizing) the interferometer phase bias of Symmetric-Mach-Zehnder (SMZ)-type ultrafast all-optical switches is proposed. In this control scheme, a weak cw light is used as a supervisory input light and its spectral power ratio at the switch output is used as a bipolar error signal. Our experimental result at 168-Gb/s 16:1 demultiplexing with a hybrid-integrated SMZ switch indicates the feasibility and the sensitivity of this control scheme.

A three-dimensional mesh generation method in which triangulation of the domain boundary is performed first is desirable since such a method would make it easier to achieve the requirements for the mesh around the boundary. We have developed a mesh generator for a 3D device simulator based on this approach. This mesh generator recursively subdivides a box that includes the whole domain into smaller boxes (cells), a method known as the octree technique. Although our mesh generator is similar to previously reported mesh generators in the sense that it utilizes recursive subdivision of elements, its major difference is that it constructs a triangular mesh upon boundaries of the domain first and this triangular mesh is not changed in the following processes. In order to generate a mesh suitable for the control volume method, a "forbidden region" is introduced and mesh points in the domain are allocated outside of this region. Since the triangular mesh is determined prior to tessellation of the domain, this method is suitable for handling layered mesh along the boundary, which is often necessary to estimate large flows parallel to the boundary precisely. A simple method to provide a layered mesh for a planar boundary is incorporated into the mesh generator. This mesh generator is integrated within our in-house three-dimensional device simulation system. The simulator's practicality is demonstrated through analysis of the reverse narrow channel effect for MOSFETs with LOCOS isolation structures. The effect of protection of the boundary by the layered mesh is also examined by calculating Id-Vg characteristics of a MOSFET with an oblique Si surface, and it is shown that protection of the whole surface of the channel region is necessary to estimate drain current correctly.

Silicon self-interstitial atom diffusion and implantation induced damage were studied by using molecular dynamics methods. The diffusion coefficient of interstitial silicon was calculated using molecular dynamics method based on the Stillinger-Weber potential. A comparison was made between the calculation method based on the Einstein relationship and the method based on a hopping analysis. For interstitial silicon diffusion, atomic site exchanges to the lattice atoms occur, and thus the total displacement-based calculation underestimates the ideal value of the diffusivity of the interstitial silicon. In addition with calculating the diffusion constant, we also identified its migration pathway and barrier energy in the case of Stillinger-Weber potential. Through a study of molecular dynamics calculation for the arsenic ion implantation process, it was found that the damage self-recovering process depends on the extent of damage. That is, damage caused by a single large impact easily disappears. In contrast, the damage leaves significant defects when two large impacts in succession cause an overlapped damage region.

Phase-Locked Loop (PLL) designers have two major problems with regard to the production of practical, portable multimedia communication systems. The first is the difficulty of achieving both fast lock time and low jitter operation simultaneously. This can be particularly difficult because the increase in loop stability needed to reduce jitter increases the lock time. The second is the problem caused by circuits operating at low voltage supplies. Low voltage supplies adversely effect the performance of phase-frequency detectors and charge pump circuits, and they can decrease the noise immunity of oscillators. We have developed a hot-standby architecture, which can achieve both fast lock time and low jitter operation simultaneously, and low-voltage circuit techniques, such as a noise-immune adaptive-gain voltage-controlled oscillator, for a fabricated PLL. This PLL is fully integrated onto a 480-µm450-µm die area with 0.18-µm CMOS technology. It can operate from 0.5 V to 1.2 V, and with a lock range from 40 MHz to 170 MHz at 0.5 V. The jitter is less than 200 ps and the lock time is less than 500 ns.