A 0.18-µm CMOS Hot-Standby PLL Using a Noise-Immune Adaptive-Gain VCO

Masayuki MIZUNO; Koichiro FURUTA; Takeshi ANDOH; Akira TANABE; Takao TAMURA; Hidenobu MIYAMOTO; Akio FURUKAWA; Masakazu YAMASHINA

A 0.18-µm CMOS Hot-Standby PLL Using a Noise-Immune Adaptive-Gain VCO

Masayuki MIZUNO, Koichiro FURUTA, Takeshi ANDOH, Akira TANABE, Takao TAMURA, Hidenobu MIYAMOTO, Akio FURUKAWA, Masakazu YAMASHINA

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Phase-Locked Loop (PLL) designers have two major problems with regard to the production of practical, portable multimedia communication systems. The first is the difficulty of achieving both fast lock time and low jitter operation simultaneously. This can be particularly difficult because the increase in loop stability needed to reduce jitter increases the lock time. The second is the problem caused by circuits operating at low voltage supplies. Low voltage supplies adversely effect the performance of phase-frequency detectors and charge pump circuits, and they can decrease the noise immunity of oscillators. We have developed a hot-standby architecture, which can achieve both fast lock time and low jitter operation simultaneously, and low-voltage circuit techniques, such as a noise-immune adaptive-gain voltage-controlled oscillator, for a fabricated PLL. This PLL is fully integrated onto a 480-µm450-µm die area with 0.18-µm CMOS technology. It can operate from 0.5 V to 1.2 V, and with a lock range from 40 MHz to 170 MHz at 0.5 V. The jitter is less than 200 ps and the lock time is less than 500 ns.

Publication: IEICE TRANSACTIONS on Electronics Vol.E80-C No.12 pp.1560-1571

Publication Date: 1997/12/25

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Type of Manuscript: Special Section PAPER (Special Issue on Low-Power and High-Speed LSI Technologies)

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Masayuki MIZUNO, Koichiro FURUTA, Takeshi ANDOH, Akira TANABE, Takao TAMURA, Hidenobu MIYAMOTO, Akio FURUKAWA, Masakazu YAMASHINA, "A 0.18-µm CMOS Hot-Standby PLL Using a Noise-Immune Adaptive-Gain VCO" in IEICE TRANSACTIONS on Electronics, vol. E80-C, no. 12, pp. 1560-1571, December 1997, doi: .
Abstract: Phase-Locked Loop (PLL) designers have two major problems with regard to the production of practical, portable multimedia communication systems. The first is the difficulty of achieving both fast lock time and low jitter operation simultaneously. This can be particularly difficult because the increase in loop stability needed to reduce jitter increases the lock time. The second is the problem caused by circuits operating at low voltage supplies. Low voltage supplies adversely effect the performance of phase-frequency detectors and charge pump circuits, and they can decrease the noise immunity of oscillators. We have developed a hot-standby architecture, which can achieve both fast lock time and low jitter operation simultaneously, and low-voltage circuit techniques, such as a noise-immune adaptive-gain voltage-controlled oscillator, for a fabricated PLL. This PLL is fully integrated onto a 480-µm450-µm die area with 0.18-µm CMOS technology. It can operate from 0.5 V to 1.2 V, and with a lock range from 40 MHz to 170 MHz at 0.5 V. The jitter is less than 200 ps and the lock time is less than 500 ns.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e80-c_12_1560/_p

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@ARTICLE{e80-c_12_1560,
author={Masayuki MIZUNO, Koichiro FURUTA, Takeshi ANDOH, Akira TANABE, Takao TAMURA, Hidenobu MIYAMOTO, Akio FURUKAWA, Masakazu YAMASHINA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 0.18-µm CMOS Hot-Standby PLL Using a Noise-Immune Adaptive-Gain VCO},
year={1997},
volume={E80-C},
number={12},
pages={1560-1571},
abstract={Phase-Locked Loop (PLL) designers have two major problems with regard to the production of practical, portable multimedia communication systems. The first is the difficulty of achieving both fast lock time and low jitter operation simultaneously. This can be particularly difficult because the increase in loop stability needed to reduce jitter increases the lock time. The second is the problem caused by circuits operating at low voltage supplies. Low voltage supplies adversely effect the performance of phase-frequency detectors and charge pump circuits, and they can decrease the noise immunity of oscillators. We have developed a hot-standby architecture, which can achieve both fast lock time and low jitter operation simultaneously, and low-voltage circuit techniques, such as a noise-immune adaptive-gain voltage-controlled oscillator, for a fabricated PLL. This PLL is fully integrated onto a 480-µm450-µm die area with 0.18-µm CMOS technology. It can operate from 0.5 V to 1.2 V, and with a lock range from 40 MHz to 170 MHz at 0.5 V. The jitter is less than 200 ps and the lock time is less than 500 ns.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - A 0.18-µm CMOS Hot-Standby PLL Using a Noise-Immune Adaptive-Gain VCO
T2 - IEICE TRANSACTIONS on Electronics
SP - 1560
EP - 1571
AU - Masayuki MIZUNO
AU - Koichiro FURUTA
AU - Takeshi ANDOH
AU - Akira TANABE
AU - Takao TAMURA
AU - Hidenobu MIYAMOTO
AU - Akio FURUKAWA
AU - Masakazu YAMASHINA
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E80-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 1997
AB - Phase-Locked Loop (PLL) designers have two major problems with regard to the production of practical, portable multimedia communication systems. The first is the difficulty of achieving both fast lock time and low jitter operation simultaneously. This can be particularly difficult because the increase in loop stability needed to reduce jitter increases the lock time. The second is the problem caused by circuits operating at low voltage supplies. Low voltage supplies adversely effect the performance of phase-frequency detectors and charge pump circuits, and they can decrease the noise immunity of oscillators. We have developed a hot-standby architecture, which can achieve both fast lock time and low jitter operation simultaneously, and low-voltage circuit techniques, such as a noise-immune adaptive-gain voltage-controlled oscillator, for a fabricated PLL. This PLL is fully integrated onto a 480-µm450-µm die area with 0.18-µm CMOS technology. It can operate from 0.5 V to 1.2 V, and with a lock range from 40 MHz to 170 MHz at 0.5 V. The jitter is less than 200 ps and the lock time is less than 500 ns.
ER -