There have been many researches on providing mobility under mobile/wireless environment. However, previous researches had several problems as disruption and unnecessary traffic. Disruption happens when messages are exchanged between nodes as registration is made after handoff, and unnecessary traffic occurs because of the use of Random-walk model, in which the probability for MN to move to the neighboring cells is equal. In order to solve these problems, this study proposes a technique and algorithm for composing Directional Shadow Registration Region (DSRR) that provides seamless mobility. The core of DSRR is to prevent disruption and unnecessary traffic by shadow registration at neighboring cells with a high probability of handoff (AAAF). We are introduced a cell division scheme and decided minimal DSRR. DSRR can sensed the optimal time for handoff through Regional Cell Division and applied Direction Vector (DV) obtained through Directional Cell Sectoring. According to the result of the experiment, the proposed DSRR processes message exchange between nodes within the intra-domain, the frequency of disruptions decreased significantly compared to that in previous researches held in inter-domain environment. In addition, traffic that occurs at every handoff happened twice in DSRR compared to n (the number of neighboring cells) times in previous researches.

As scaling has been continued more than 20 years, it has yielded faster and denser chips with ever increasing functionality. The scaling will continue down to or beyond 0.1 µm as proposed in SIA Technical Road map. With scaling, device performance improves, however, interconnect performance is degraded. In this scaled deep submicron technology, however, interconnects limit the performance, packing density and yield, if not properly modeled. In order to properly model and design the interconnect-dominated circuits, accurate and proper interconnect modeling is a must to assure the performance and functionality of ever-increasing complex multi-million transistor VLSI circuits. In this paper, the overall flow of interconnect modeling in IC design is reviewed including interconnect characterization, various 2-D/3-D field solvers, 2-D/3-D interconnect model library generation, and parameter extraction. And advanced topics of interconnect modeling in deep submicron are reviewed; statistical interconnect modeling.