Interconnect Modeling in Deep-Submicron Design
Summary :
As scaling has been continued more than 20 years, it has yielded faster and denser chips with ever increasing functionality. The scaling will continue down to or beyond 0.1 µm as proposed in SIA Technical Road map. With scaling, device performance improves, however, interconnect performance is degraded. In this scaled deep submicron technology, however, interconnects limit the performance, packing density and yield, if not properly modeled. In order to properly model and design the interconnect-dominated circuits, accurate and proper interconnect modeling is a must to assure the performance and functionality of ever-increasing complex multi-million transistor VLSI circuits. In this paper, the overall flow of interconnect modeling in IC design is reviewed including interconnect characterization, various 2-D/3-D field solvers, 2-D/3-D interconnect model library generation, and parameter extraction. And advanced topics of interconnect modeling in deep submicron are reviewed; statistical interconnect modeling.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E83-C No.8 pp.1311-1316
- Publication Date
- 2000/08/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section INVITED PAPER (Special Issue on 1999 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'99))
- Category
- Circuit Applications
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Won-Young JUNG, Soo-Young OH, Jeong-Taek KONG, Keun-Ho LEE, "Interconnect Modeling in Deep-Submicron Design" in IEICE TRANSACTIONS on Electronics,
vol. E83-C, no. 8, pp. 1311-1316, August 2000, doi: .
Abstract: As scaling has been continued more than 20 years, it has yielded faster and denser chips with ever increasing functionality. The scaling will continue down to or beyond 0.1 µm as proposed in SIA Technical Road map. With scaling, device performance improves, however, interconnect performance is degraded. In this scaled deep submicron technology, however, interconnects limit the performance, packing density and yield, if not properly modeled. In order to properly model and design the interconnect-dominated circuits, accurate and proper interconnect modeling is a must to assure the performance and functionality of ever-increasing complex multi-million transistor VLSI circuits. In this paper, the overall flow of interconnect modeling in IC design is reviewed including interconnect characterization, various 2-D/3-D field solvers, 2-D/3-D interconnect model library generation, and parameter extraction. And advanced topics of interconnect modeling in deep submicron are reviewed; statistical interconnect modeling.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e83-c_8_1311/_p
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@ARTICLE{e83-c_8_1311,
author={Won-Young JUNG, Soo-Young OH, Jeong-Taek KONG, Keun-Ho LEE, },
journal={IEICE TRANSACTIONS on Electronics},
title={Interconnect Modeling in Deep-Submicron Design},
year={2000},
volume={E83-C},
number={8},
pages={1311-1316},
abstract={As scaling has been continued more than 20 years, it has yielded faster and denser chips with ever increasing functionality. The scaling will continue down to or beyond 0.1 µm as proposed in SIA Technical Road map. With scaling, device performance improves, however, interconnect performance is degraded. In this scaled deep submicron technology, however, interconnects limit the performance, packing density and yield, if not properly modeled. In order to properly model and design the interconnect-dominated circuits, accurate and proper interconnect modeling is a must to assure the performance and functionality of ever-increasing complex multi-million transistor VLSI circuits. In this paper, the overall flow of interconnect modeling in IC design is reviewed including interconnect characterization, various 2-D/3-D field solvers, 2-D/3-D interconnect model library generation, and parameter extraction. And advanced topics of interconnect modeling in deep submicron are reviewed; statistical interconnect modeling.},
keywords={},
doi={},
ISSN={},
month={August},}
Copy
TY - JOUR
TI - Interconnect Modeling in Deep-Submicron Design
T2 - IEICE TRANSACTIONS on Electronics
SP - 1311
EP - 1316
AU - Won-Young JUNG
AU - Soo-Young OH
AU - Jeong-Taek KONG
AU - Keun-Ho LEE
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E83-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2000
AB - As scaling has been continued more than 20 years, it has yielded faster and denser chips with ever increasing functionality. The scaling will continue down to or beyond 0.1 µm as proposed in SIA Technical Road map. With scaling, device performance improves, however, interconnect performance is degraded. In this scaled deep submicron technology, however, interconnects limit the performance, packing density and yield, if not properly modeled. In order to properly model and design the interconnect-dominated circuits, accurate and proper interconnect modeling is a must to assure the performance and functionality of ever-increasing complex multi-million transistor VLSI circuits. In this paper, the overall flow of interconnect modeling in IC design is reviewed including interconnect characterization, various 2-D/3-D field solvers, 2-D/3-D interconnect model library generation, and parameter extraction. And advanced topics of interconnect modeling in deep submicron are reviewed; statistical interconnect modeling.
ER -
English
