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[Author] Itthichai ARUNGSRISANGCHAI(2hit)

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  • A Fast Minimum Cost Flow Algorithm for Regenerating Optimal Layout of Functional Cells

    Itthichai ARUNGSRISANGCHAI  Yuji SHIGEHIRO  Isao SHIRAKAWA  Hiromitsu TAKAHASHI  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E80-A No:12
      Page(s):
    2589-2599

    A new flow algorithm is described on the basis of the primal-dual method, which is to be adopted dedicatedly for the regeneration of optimal layouts for functional cells of the standard-cell level. In advance of discussing this main theme, the present paper first outlines a practical scheme of reusing those layouts which have been once generated for functional cells in an old fabrication technology, and then formulates an optimization problem for regenerating optimal layouts of functional cells under the constraints incurred by the renewal of design rules. An efficient algorithm proposed here aims at solving this optimization problem with the use of solution concepts for the minimum cost flow problem. A part of experimental results is also shown, which indicates that the proposed altorithm is the fastest for this optimization problem.

  • An Automatic Layout Generator for Bipolar Analog Modules

    Takao ONOYE  Akihisa YAMADA  Itthichai ARUNGSRISANGCHAI  Masakazu TANAKA  Isao SHIRAKAWA  

     
    PAPER

      Vol:
    E75-A No:10
      Page(s):
    1306-1314

    An autonatic layout scheme dedicated to bipolar analog modules is described. A layout model is settled in such a way that the VCC/GND line is laid out on top/bottom edge of a rectangular region, within which the whole elements are placed and interconnected. According to this simple modeling, a layout scheme can be constructed of a series of the following algorithms: First clustering is executed for partitioning a given circuit into clusters, each having connections with VCC and GND lines, and then linear ordering is applied to clusters so as to be placed in a one-dimensional array. After a relative placement of circuits elements in each cluster, a block compactor is implemented by means of packing blocks in each cluster into an idle space, and then a detailed router is conducted to attain 100% interconnection. Finally a layout compactor is invoked to pack all layout patterns into a rectangle of the minimum possible area. A number of implementation results are also shown to reveal the practicability of the proposed analog module generator.