Area-Efficient Reconfigurable Architecture for Media Processing

Yukio MITSUYAMA; Kazuma TAKAHASHI; Rintaro IMAI; Masanori HASHIMOTO; Takao ONOYE; Isao SHIRAKAWA

doi:10.1093/ietfec/e91-a.12.3651

Area-Efficient Reconfigurable Architecture for Media Processing

Yukio MITSUYAMA, Kazuma TAKAHASHI, Rintaro IMAI, Masanori HASHIMOTO, Takao ONOYE, Isao SHIRAKAWA

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An area-efficient dynamically reconfigurable architecture is proposed, which is dedicated to media processing. To implement a compact but high performance device, which can be used in consumer applications, the reconfigurable architecture distinctively performs 8-bit operations required for media processing whereas fine-grained operations are executed with the cooperation of a host processor. A heterogeneous reconfigurable array is composed of four types of cells, for which configuration data size is reduced by focusing application domain on media processing. Implementation results show that a multi-standard video decoding can be achieved by the proposed reconfigurable architecture with 1.11.4 mm² in a 90 nm CMOS technology.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E91-A No.12 pp.3651-3662

Publication Date: 2008/12/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1093/ietfec/e91-a.12.3651

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category: Embedded, Real-Time and Reconfigurable Systems

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Yukio MITSUYAMA, Kazuma TAKAHASHI, Rintaro IMAI, Masanori HASHIMOTO, Takao ONOYE, Isao SHIRAKAWA, "Area-Efficient Reconfigurable Architecture for Media Processing" in IEICE TRANSACTIONS on Fundamentals, vol. E91-A, no. 12, pp. 3651-3662, December 2008, doi: 10.1093/ietfec/e91-a.12.3651.
Abstract: An area-efficient dynamically reconfigurable architecture is proposed, which is dedicated to media processing. To implement a compact but high performance device, which can be used in consumer applications, the reconfigurable architecture distinctively performs 8-bit operations required for media processing whereas fine-grained operations are executed with the cooperation of a host processor. A heterogeneous reconfigurable array is composed of four types of cells, for which configuration data size is reduced by focusing application domain on media processing. Implementation results show that a multi-standard video decoding can be achieved by the proposed reconfigurable architecture with 1.11.4 mm² in a 90 nm CMOS technology.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e91-a.12.3651/_p

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@ARTICLE{e91-a_12_3651,
author={Yukio MITSUYAMA, Kazuma TAKAHASHI, Rintaro IMAI, Masanori HASHIMOTO, Takao ONOYE, Isao SHIRAKAWA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Area-Efficient Reconfigurable Architecture for Media Processing},
year={2008},
volume={E91-A},
number={12},
pages={3651-3662},
abstract={An area-efficient dynamically reconfigurable architecture is proposed, which is dedicated to media processing. To implement a compact but high performance device, which can be used in consumer applications, the reconfigurable architecture distinctively performs 8-bit operations required for media processing whereas fine-grained operations are executed with the cooperation of a host processor. A heterogeneous reconfigurable array is composed of four types of cells, for which configuration data size is reduced by focusing application domain on media processing. Implementation results show that a multi-standard video decoding can be achieved by the proposed reconfigurable architecture with 1.11.4 mm² in a 90 nm CMOS technology.},
keywords={},
doi={10.1093/ietfec/e91-a.12.3651},
ISSN={1745-1337},
month={December},}

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TY - JOUR
TI - Area-Efficient Reconfigurable Architecture for Media Processing
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3651
EP - 3662
AU - Yukio MITSUYAMA
AU - Kazuma TAKAHASHI
AU - Rintaro IMAI
AU - Masanori HASHIMOTO
AU - Takao ONOYE
AU - Isao SHIRAKAWA
PY - 2008
DO - 10.1093/ietfec/e91-a.12.3651
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E91-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2008
AB - An area-efficient dynamically reconfigurable architecture is proposed, which is dedicated to media processing. To implement a compact but high performance device, which can be used in consumer applications, the reconfigurable architecture distinctively performs 8-bit operations required for media processing whereas fine-grained operations are executed with the cooperation of a host processor. A heterogeneous reconfigurable array is composed of four types of cells, for which configuration data size is reduced by focusing application domain on media processing. Implementation results show that a multi-standard video decoding can be achieved by the proposed reconfigurable architecture with 1.11.4 mm² in a 90 nm CMOS technology.
ER -