A digital filter is one of the fundamental elements in the digital video transmission, and a multiplier acts as the key factor that determines the operation speed and silicon area of the filter. In terms of the digital video transmission, the required performance of a multiplier is to operate at the speed of 20-100 MHz but with the precision of 8-10 bits. In the case of implementing such an FIR filter with more than a certain number of taps, the same number of multipliers are necessary to realize the speed. Moreover, even though the coefficients to the filter are desired to be programmable, it is possible to change coefficients in the vertical fly-back interval of television receivers. This allows the preloadability of coefficients to the filter such that each coefficient can be treated as a constant during the filtering operation. Motivated by these requirements and functionalities, a novel multiplier and FIR filter architecture is described, which is to be synthesized with the use of a high level synthesis tool of COMPASS Design Navigator, partly with the aid of the manual design by means of a 0.8µm CMOS library.