A High Performance Multiplier and Its Application to an FlR Filter Dedicated to Digital Video Transmission

Keisuke OKADA; Shun MORIKAWA; Sumitaka TAKEUCHI; Isao SHIRAKAWA

A High Performance Multiplier and Its Application to an FlR Filter Dedicated to Digital Video Transmission

Keisuke OKADA, Shun MORIKAWA, Sumitaka TAKEUCHI, Isao SHIRAKAWA

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A digital filter is one of the fundamental elements in the digital video transmission, and a multiplier acts as the key factor that determines the operation speed and silicon area of the filter. In terms of the digital video transmission, the required performance of a multiplier is to operate at the speed of 20-100 MHz but with the precision of 8-10 bits. In the case of implementing such an FIR filter with more than a certain number of taps, the same number of multipliers are necessary to realize the speed. Moreover, even though the coefficients to the filter are desired to be programmable, it is possible to change coefficients in the vertical fly-back interval of television receivers. This allows the preloadability of coefficients to the filter such that each coefficient can be treated as a constant during the filtering operation. Motivated by these requirements and functionalities, a novel multiplier and FIR filter architecture is described, which is to be synthesized with the use of a high level synthesis tool of COMPASS Design Navigator, partly with the aid of the manual design by means of a 0.8µm CMOS library.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E79-A No.12 pp.2106-2111

Publication Date: 1996/12/25

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Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

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Keisuke OKADA, Shun MORIKAWA, Sumitaka TAKEUCHI, Isao SHIRAKAWA, "A High Performance Multiplier and Its Application to an FlR Filter Dedicated to Digital Video Transmission" in IEICE TRANSACTIONS on Fundamentals, vol. E79-A, no. 12, pp. 2106-2111, December 1996, doi: .
Abstract: A digital filter is one of the fundamental elements in the digital video transmission, and a multiplier acts as the key factor that determines the operation speed and silicon area of the filter. In terms of the digital video transmission, the required performance of a multiplier is to operate at the speed of 20-100 MHz but with the precision of 8-10 bits. In the case of implementing such an FIR filter with more than a certain number of taps, the same number of multipliers are necessary to realize the speed. Moreover, even though the coefficients to the filter are desired to be programmable, it is possible to change coefficients in the vertical fly-back interval of television receivers. This allows the preloadability of coefficients to the filter such that each coefficient can be treated as a constant during the filtering operation. Motivated by these requirements and functionalities, a novel multiplier and FIR filter architecture is described, which is to be synthesized with the use of a high level synthesis tool of COMPASS Design Navigator, partly with the aid of the manual design by means of a 0.8µm CMOS library.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e79-a_12_2106/_p

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@ARTICLE{e79-a_12_2106,
author={Keisuke OKADA, Shun MORIKAWA, Sumitaka TAKEUCHI, Isao SHIRAKAWA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A High Performance Multiplier and Its Application to an FlR Filter Dedicated to Digital Video Transmission},
year={1996},
volume={E79-A},
number={12},
pages={2106-2111},
abstract={A digital filter is one of the fundamental elements in the digital video transmission, and a multiplier acts as the key factor that determines the operation speed and silicon area of the filter. In terms of the digital video transmission, the required performance of a multiplier is to operate at the speed of 20-100 MHz but with the precision of 8-10 bits. In the case of implementing such an FIR filter with more than a certain number of taps, the same number of multipliers are necessary to realize the speed. Moreover, even though the coefficients to the filter are desired to be programmable, it is possible to change coefficients in the vertical fly-back interval of television receivers. This allows the preloadability of coefficients to the filter such that each coefficient can be treated as a constant during the filtering operation. Motivated by these requirements and functionalities, a novel multiplier and FIR filter architecture is described, which is to be synthesized with the use of a high level synthesis tool of COMPASS Design Navigator, partly with the aid of the manual design by means of a 0.8µm CMOS library.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - A High Performance Multiplier and Its Application to an FlR Filter Dedicated to Digital Video Transmission
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2106
EP - 2111
AU - Keisuke OKADA
AU - Shun MORIKAWA
AU - Sumitaka TAKEUCHI
AU - Isao SHIRAKAWA
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E79-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 1996
AB - A digital filter is one of the fundamental elements in the digital video transmission, and a multiplier acts as the key factor that determines the operation speed and silicon area of the filter. In terms of the digital video transmission, the required performance of a multiplier is to operate at the speed of 20-100 MHz but with the precision of 8-10 bits. In the case of implementing such an FIR filter with more than a certain number of taps, the same number of multipliers are necessary to realize the speed. Moreover, even though the coefficients to the filter are desired to be programmable, it is possible to change coefficients in the vertical fly-back interval of television receivers. This allows the preloadability of coefficients to the filter such that each coefficient can be treated as a constant during the filtering operation. Motivated by these requirements and functionalities, a novel multiplier and FIR filter architecture is described, which is to be synthesized with the use of a high level synthesis tool of COMPASS Design Navigator, partly with the aid of the manual design by means of a 0.8µm CMOS library.
ER -