The pros and cons of CDMA as a multiple access scheme for third generation cellular mobile radio systems are considered. Main criteria are spectral efficiency and capacity, but also flexibility and costs.

Research and standardization activities on FPLMTS are under way throughout the world. This paper shows recent study results on radio transmission technologies in ARIB (Association of Radio Industries and Businesses), which in the standardization organization in Japan. On-going study shows two TDMA based and four CDMA based radio transmission technologies under study. These technologies need to be further studied in detail. The proposal from ARIB is expected to be summarized around the end of the year 1996.

New interference cancellation technique using time division reference signal is proposed for optical synchronous code-division multiple-access (CDMA) systems with modified prime sequence codes. In the proposed system one user in each group is not allowed to access the network at each time, and this unallowable user's channel is used as a reference signal for other users in the same group at the time. The performance of the proposed system using an avalanche photodiode (APD) is analyzed where the Gaussian approximation of the APD output is employed and the effects of APD noise, thermal noise, and interference for the receiver are included. The proposed cancellation techniqus is shown to be effective to improve the bit error probability performance and to alleviate the error floor when the number of users and the received optical power are not appreciably small.

This paper deals with performance evaluation of CDMA based on DS/SS/GMSK signaling with the differential detection over multipath Rayleigh fading channels. To demodulate DS/SS/GMSK signals, we consider differential detection, which does not need a carrier recovery. The bit-error-rate performance is evaluated in the presence of thermal noise and multipleaccess interferences under the multipath Rayleigh fading environment. To improve the performance, we also consider adoption of a RAKE receiver.

In this paper, a multiuser receiver using a Hopfield network (Hopfield network receiver) for asynchronous codedivision multiple-access systems is proposed. We derive a novel likelihood function for the optimum demodulation of a data subsequence whose length is far shorter than that of the entire transmitted data sequence. It is shown that a novel Hopfield network receiver can be derived by exploiting the likelihood function, and the derived receiver leads to a low complexity receiver. The structure of the proposed receiver consists of a bank of correlators and a Hopfield network where the number of units is proportional to both the number of users and the length of a data sequence demodulated at a time. Computer simulation results are presented to compare the performance of the proposed receiver with those of the conventional multiuser detectors. It is shown that the proposed receiver significantly outperforms the correlation receiver, decorrelating detector and multistage detector, and provides suboptimum performnace.

In this paper, we describe effects of oddcorrelation functions and band-limitation filters for direct-wave reception systems using broadband spread-spectrum (B-SS) techniques. The receiver of this system is synchronized to the direct-wave. First, the effects of odd-correlation functions are investigated by using M-sequences and random sequences. The effects of even-correlation functions for those sequences can be easily obtained by using results of effects of odd-correlation functions for random sequences. Here we derive a novel function of odd-correlation variance for M-sequence, which is obtained theoretically. Consequently, we show the advantage of M-sequence which is used as spreading sequence. As a reason, in the odd-correlation function of M-sequence, small values are taken near the synchronous phase where harmful scattered-waves exist, strongly. Next, the effects of both odd-correlation function and band-limitation filter are studied by using several kinds of filters. Here we discuss the difference of characteristics in case that despreading sequence of bandlimited pulse or that of rectangular pulse is used in the correlator of the receiver. The technique despreading by rectangular pulse can be achieved a high speed signal processing and equipment miniaturizing because of utilization of switching circuit. We show the advantage of despreading sequence of rectangular pulse, when the limitation bandwidth of transmitting signal takes a small value. Because the characteristics of the correlation function between transmitting sequence of bandlimited pulse and despreading sequence of rectangular pulse can be kept better than that between the transmitting sequence and despreading sequence of bandlimited pulse. As these results, in severe bandlimited direct-wave reception systems using B-SS techniques, M-sequence of rectangular pulse as despreading sequence is most suitable.

In this paper, the bit error rate (BER) considering tracking performance is evaluated, by theoretical analysis and computer simulation, for a bi-orthogonal system using a synchronizing pseudo-noise (PN) sequence and co-channel interference cancellers. A system that improves on Tachikawa's system is proposed. It is found that the optimum ratio of the information signal energy to the synchronizing signal energy varies with E_b/N_o, and the canceller is better for small L than for large L (L = length of the sequence). Moreover, it is found that the BER considering synchronization performance improvse as the equivalent noise bandwidth B_n decreases.

In this paper, a simple frame synchronization system for M-ary/SS communication systems is proposed, and synchronization performance and the resulting bit error rate performance are analyzed. The frame synchronization system uses racing counters and framing chips which are added to spreading sequences. M-ary/SS communication systems can improve bit error rate performance under the condition in which there is an additive white gaussian noise. Synchronization of M-ary/SS communication systems is difficult, however, because M-ary/SS communication systems have several spreading sequences. The authors proposed the simple frame synchronization system which uses only one chip in the spreading sequence as a framing signal. This system needs a long time for initial acquisition as the frame length is longer. The proposed system in this paper can make initial acquisition time short by increasing the number of framing chips. The proposed system corresponds to the conventional system when the number of framing chips is l. As the result, it is shown that several framing chips contribute to decrease the initial acquisition time. Moreover, the frame synchronization system can be applied to asynchronous M-ary/SSMA system when different framing chip pattern is assigned to each user.

This paper evaluates the performance of DS/CDMA with diversity coding and multiuser interference (MUI) cancellation in fading multipath channel. The diversity technique considered in this paper, is different from the conventional scheme and transmits different information over different channels. It is shown that, this diversity scheme performs better than conventional diversity scheme, and when combined with MUI cancellation provides significant performance improvement. Effects of partial band jamming on the system are also considered.

Capacity of Cellular DS/CDMA systems depends on an amount of co-channel interference (CCI). One of the effective schemes to eliminate the CCI and improve the capacity is CCI cancellers which remove the CCI by subtracting all the regenerated signals of the interfering users. These cancellers, however, suffer from the residual interference due to the symbol errors in the initial decision. Therefore, a canceller which employed error correction in the initial decision has been proposed. In this system, two Viterbi decoders per one user are needed. Therefore, the amount of calculation increases and this causes additional signal processing delay which is not preferable, especially for voice transmission. Here we propose three fast decoding methods by simplifying the second Viterbi decoder which is used for decoding after the cancellation. Method-1 uses information of the first Viterbi decoder. Method-2 utilizes information of the second correlator instead of that of the first Viterbi decoder. Method-3 is the combination of method-1 and method-2. It uses information from both the first Viterbi decoder and the second correlator. The results obtained from the computer simulation show that the ACS reduction ratio reaches up to 80% within 0.5 dB degradation in E_s/N_o.

In this contribution an algorithm for joint detection in fast frequency hopping/multiple frequency shift keying (FFH/MFSK) multiple access (MA) systems is presented. The new algorithm - referred to as REC algorithm - evaluates ambiguities which occur during the decision process and iteratively reduces the number of candidate symbols. The REC algorithm is of low complexity, suitable for every addressing scheme, and effective for both an interference-only channel and a fading channel. For the interference-only channel the REC algorithm enables maximum likelihood (ML) joint detection with low computational effort.

When wireless multi-media information which includes speech, image, data and so on are transmitted, the defference in information rate, required quality as well as traffic performance should be taken into account. A wireless spread spectrum system can achieve a flexible balance of these differences because of the inherent asynchronous capability of CDMA. In this paper, we propose a wireless multi-media CDMA system based on a processing gain control in a dynamic traffic channel. According to the priority of each medium and channel measurement information i.e. traffic, the optimal processing gain can be controlled by using Nonlinear Programming. Numerical results demonstrate that the proposed method possesses higher flexible capacity than TDMA in a dynamic multi-medea traffic channel.

A simplified analysis is presented for the reverse link capacity of DS-CDMA mobile radio with transmit power control (TPC) based on measurement of signal-to-interference plus background noise (SIR) when users require different levels of quality. The link capacity is defined as the maximum achievable sum of the required SIRs, and the increase in transmit power due to SIR-based TPC is discussed. Also analyzed is the total link capacity when narrowband DS-CDMA systems share the radio spectrum of a wideband system. The capacity loss due to non-uniform use of the spectrum is discussed.

The one of the problems in the satellite packet communication system is the existence of a long time delay, which may cause an improper packet access control resulting in a great deal of degradation of the system performance. In this paper, we clarify the effect of long time delay on the performance of CDMA ALOHA systems and then propose a new access control protocol, called Modified Channel Load Sensing Protocol (MCLSP), for the CDMA ALOHA systems. As a result, we show that a significant improvement in the throughput performance was obtained with MCLSP even in the presence of a long time delay.

This paper examines the performance of a direct sequence, spread spectrum (DSSS) multiple access (MA) system used over two typical, frequency-selective, fading satellite channels. In an attempt to increase the system efficiency, an adaptive receiver described by Rapajic and Vucetic [1] has been implemented. This system has been combined with soft-decision convolutional coding in order to improve the system performance under the fading conditions relative to the uncoded system and to allow as many simultaneous users as possible. Various code rates have been examined and the results are given. This paper specifically focuses on DSSS-MA systems with low spreading ratios. The satellite channels used in this paper were produced by models developed as a result of experimental measurements of fading satellite channels for rural and urban environments.

In the envisaged Universal Mobile Telecommunications System (UMTS), the satellite component will have to provide services to mobile or, in some cases, hand held terminals with a required grade of user co-operation and link availability in various communication environments. This may require the capability of the satellite link to cope with more severe multipath environments than those for which mobile satellite links are most frequently designed (maritime or open rural applications); unfortunately, when the mobile radio channel is affected by multipath and a coherent demodulation is chosen, the phase synchronisation can be a critical issue. To satisfactorily deal with the arising difficulties, a dual channel demodulation is a viable and efficient strategy for the forward link, since only one common pilot channel is needed in this case. If the same dual channel demodulation is considered for the return link, an unacceptable capacity reduction may result. In this paper, some synchronisation strategies are analysed and an efficient dual channel demodulation scheme is proposed for the return link of a satellite DS-CDMA mobile communication system; furthermore, the impact on the overall system performance or capacity is analysed.

In this paper we propose a direct sequence spread spectrum (DS/SS) modulation method which employs Gaussian-filtered minimum shift keying (GMSK) and permits simple code acquisition. A transmitter which includes a conventional GMSK modulator and pseudo-noise (PN) code generator can achieve the proposed modulation method. The received signal can be demodulated by four-phase correlator which can obtain the correlation value of received signal even if phase difference exists between the transmitter and the receiver. The modulation method employs phase-shift-keying (PSK) by modulating the phase of transmitted PN code for data transmission. We carried out hardware experiments and the measured bit error performance ensures the validity of this modulation method. Then we designed and developed a demodulator LSI which is applicable to a modulation method such as the DS/GMSK/PSK. The LSI is suitable for demodulation of spreadspectrum signal which can be demodulated by four-phase correlator.

A matched filter (Mf) based on analog filter technology for DS-CDMA mobile radio is presented. An experimental one-chip LSI of AMF is developed for measuring various areas of performance such as power consumption, cut-off frequency, and linearity. The measurements show that power consumption is only 110mW at a voltage supply of 3V and an operational clock frequency of 25 MHz. We implemented a RAKE combiner using experimental AMF LSI and measured the bit error rate (BER) performance of DS-CDMA signal transmission in a multipath fading environment.

In this paper, the bit error rate (BER) performance of the Spread Spectrum communication system with Constrained Spreading Codes (SS-CSC) is analyzed. The BER of the SS-CSC system is the same as that of the Bi-orthogonal system. Moreover, the frequency utilization efficiency of the SS-CSC system is better than that of the Bi-orthogonal system when K 10 and N = 3.

In this letter, we propose a blind adaptive receiver with nonlinear structure for DS/CDMA communication systems. The proposed receiver requires the signature waveform and timing for only the desired user. It is shown that the blind adaptation is equivalent to the adaptation with the training signal and the function to be minimized has no local minima.

In this paper, a design of a new processor array architecture with effective data storage schemes which meets the practical requirement of a reduced number of processor elements is proposed. Its design method is shown to be drastically simpler than the popular systolic arrays. This processor array which we call Memory Sharing Processor Array (MSPA) consists of a processor array, several memory units, and some address generation hardware units used to minimize the number of I/O ports. MSPA architecture with its design methodology tries to overcome overlapping data storages, idle processing time and I/O bottleneck problems, which mostly degrade the performance of systolic architecture. It has practical advantages over the systolic array in the view of area-efficiency, high throughput and practical input schemes.

Memory Sharing Processor Array (MSPA) architecture has been developed as an effective array processing architecture for both reduced data storages and increased processor cell utilization efficiency [1]. In this paper, the MSPA design methodology is extended to the VLSI synthesis of a serial input processor array (Pa). Then, a new bit-serial input multiplier and a new data serial input matrix multiplier are derived from the new PA. These multipliers are superior to the conventional multipliers by their smaller number of logic-gate count.

A digital filter is one of the fundamental elements in the digital video transmission, and a multiplier acts as the key factor that determines the operation speed and silicon area of the filter. In terms of the digital video transmission, the required performance of a multiplier is to operate at the speed of 20-100 MHz but with the precision of 8-10 bits. In the case of implementing such an FIR filter with more than a certain number of taps, the same number of multipliers are necessary to realize the speed. Moreover, even though the coefficients to the filter are desired to be programmable, it is possible to change coefficients in the vertical fly-back interval of television receivers. This allows the preloadability of coefficients to the filter such that each coefficient can be treated as a constant during the filtering operation. Motivated by these requirements and functionalities, a novel multiplier and FIR filter architecture is described, which is to be synthesized with the use of a high level synthesis tool of COMPASS Design Navigator, partly with the aid of the manual design by means of a 0.8µm CMOS library.

A 3V-50 MHz analog CMOS current-mode continuous-time active filter with a negative resistance load (NRL) is proposed. In order to design a current-mode current integrator, a modified basic current mirror with a NRL to increase the output resistance is employed. The inherent circuit structure of the designed NRL current integrator, which minimizes the internal circuit nodes and enhances the gain bandwidth product, is capable of making the filter operate at the high frequency. The third order Butterworth low pass filter utilizing the designed NRL current integrator is synthesized and simulated with a 1.5 µm CMOS n-well process. Simulation result shows the cutoff frequency of 50 MHz and power consumption of 2.4mW/pole with a 3V power supply.

This paper describes new problems in delay analysis for high-performance LSI design and presents a static delay analysis tool PCHECK. PCHECK is characterized by (1) a new critical path trace algorithm for avoiding the error caused by signal transient time and (2) a precise delay calculation model for resistive shielding. Experimental results show that the delay calculation error in the worst case is less than 20 ps.

A generalized Reed-Muller expression (GRM) is obtained by negating some of the literals in a positive polarity Reed-Muller expression (PPRM). There are at most 2^{(n2)^(n-1)} different GRMs for an n-variable function. A minimum GRM is one with the fewest products. This paper presents certain properties and an exact minimization algorithm for GRMs. The minimization algorithm uses binary decision diagrams. Up to five variables, all the representative functions of NP-equivalence classes were generated and minimized. Tables compare the number of products necessary to represent four-and five-variable functions for four classes of expressions: PPRMs, FPRMs, GRMs and SOPs. GRMs require, on the average, fewer products than sum-of-products expressions (SOPs), and have easily testable realizations.

In this paper, an exact-minimization method for an AND-EXOR expression (ESOP) using O-suppressed binary decision diagrams (ZBDDs) is considered. The proposed method is an improvement of Sasao's MRCF-based method. From experimental results, it is shown that required ZBDD size is reduced to 1/3 in the best case compared with the MRCF-based method.

Recently, various efficient algorithms for solving combinatorial optimization problems using BDD-based set manipulation techniques have been developed. Minato proposed O-suppressed BDDs (ZBDDs) which is suitable for set manipulation, and it is utilized for various search problems. In terms of practical limits of space, however, there are still many search problems which are solved much better by using conventional branch-and-bound techniques than by using BDDs or ZBDDs, while the ability of conventional branch-and-bound approaches is limited by computation time. In this paper, an extension of APPLY operation, named APPRUNE (APply + PRUNE) operation, is proposed, which performs APPLY operation (ZBDD construction) and pruning simultaneously in order to reduce the required space for intermediate ZBDDs. As a prototype, a specific algorithm of APPRUNE operation is shown by assuming that the given condition for pruning is a threshold function, although it is expected that APPRUNE operation will be more effective if more sophisticated condition are considered. To reduce size of ZBDDs in intermediate steps, this paper also pay attention to the number of cared variables. As an application, an exact-minimization algorithm for generalized Reed-Muller expressions (GRMs) is implemented. From experimental results, it is shown that time and memory usage improved 8.8 and 3.4 times, respectively, in the best case using APPRUNE operation. Results on generating GRMs of exact-minimum number of not only product terms but also literals is also shown.

Transport-processing FPGAs have been proposed for flexible telecommunication systems. Since those FPGAs have finer granularity of logic functions to implement circuits on them, the amount of routing resources tends to increase. In order to keep routing congstion small, it is necessary to execute placement and routing simultaneously. This paper proposes a simultaneous placement and global routing algorithm for transport-processing FPGAs whose primary objective is minimizing routing congestion. The algorithm is based on hierarchical bipartition of layout regions and sets of LUTs (Look Up Tables) to be placed. It achieves bipartitioning which leads to small routing congestion by applying a network flow technique to it and computing a maximum flow and a minimum cut. If there exist connections between bipartitioned LUT sets, pairs of pseudo-terminals are introduced to preserve the connections. A sequence of pseudo-terminals represents a global route of each net. As a result, both placement of LUTs and global routing are determined when hierarchical bipartitioning procedures are finished. The proposed algorithm has been implemented and applied to practical transport-processing circuits. The experimental results demonstrate that it decreases routing congestion by an average of 37% compared with a conventional algorithm and achieves 100% routing for the circuits for which the conventional algorithm causes unrouted nets.

In this paper, a new spectral subtraction technique with two microphone inputs is proposed. In conventional spectral subtraction using a single microphone, the averaged noise spectrum is subtracted from the observed short-time input spectrum. This results in reduction of mean value of noise spectrum only, the component varying around the mean value remaining intact. In the method proposed in this paper, the short-time noise spectrum excluding the speech component is estimated by introducing the blocking matrix used in the Griffiths-Jim-type adaptive beamformer with two microphone inputs, combined with the spectral compensation technique. By subtracting the estimated short-time noise spectrum from the input spectrum, not only the mean value of the noise spectrum but also the component varying around the mean value can be reduced. This method can be interpreted as a partial construction of the adaptive beamformer where only the amplitude of the short-time noise spectrum is estimated, while the adaptive beamformer is equivalent to the estimator of the complex short-time noise spectrum. By limiting the estimation to the amplitude spectrum, the proposed system achieves better performance than the adaptive beamformer in the case when the number of sound sources exceeds the number of microphones.

This paper describes an N-type and a P-type MOS cascode circuit based on the square-law characteristics of an MOS transistor in saturation region. The transconductance parameter ratios of an upper and a lower MOS transistor are set to be 1: n² for the N-type MOS cascode circuit and n²: 1 for the P-type MOS cascode circuit. The N and P-type MOS cascode circuits are divided to four types by the difference of connections of input terminals. We consider the input-output relations of each type circuit. The second-order effects of the circuit such as channel length modulation effect, mobility reduction effect and device mismatch are analyzed. As applications, an analog voltage adder and a V_T level shifter using MOS cascode circuits are presented. All of the proposed circuits are very simple and consist of only the N and P-type MOS cascode circuits. The proposed circuits aer confirmed by SPICE simulation with MOSIS 1.2µm CMOS process parameters.

In this paper stochastic aradient adaptive filters using the Sign or Sign-Sign Algorithm are analyzed based upon general assumptions on the reference signal, additive noise and particularly jointly distributed tap errors. A set of difference equations for calculating the convergence process of the mean and covariance of the tap errors is derived with integrals involving characteristic function and its derivative of the tap error distribution. Examples of echo canceller convergence with jointly Gaussian distributed tap errors show an excellent agreement between the empirical results and the theory.

This paper presents a new method for the selftuning control of nonminimum phase discrete-time stochastic systems using approximate inverse systems obtained from the leastsquares approximation. Using this approximate inverse system the gain response of the system can be made approximately unit and phase response exactly zero. We show how unstable polezero cancellations can be avoided. This approximate inverse system can be used in the same manner for both minimum and nonminimum phase systems. Moreover, the degrees of the controller polynomials do not depend on the approximate inverse system. We just need an extra FIR filter in the feedforward path.

In this paper, we propose a clustering based linear ordering algorithm which consists of global ordering and local ordering. In the global ordering, the algorithm forms clusters from n given vertices and orders the clusters. In the local ordering, the elements in each cluster are linearly ordered. The linear order, thus produced, is used to obtain optimal κ-way partitioning based on scaled cost objective function. When the number of cluster is one, the proposed algorithm is exactly the same as MELO [2]. But the proposed algorithm has more global partitioning information than MELO by clustering. Experiment with 11 benchmark circuits for κ-way (2 κ 10) partitioning shows that the proposed algorithm yields an average of 10.6% improvement over MELO [2] for the κ-way scaled cost partitioning.

This paper deals with the synthesis of Petri nets. Partial languages adequately represent the concurrent behaviors of Petri nets. We first propose a construction problem for Petri nets, in which the objective is to synthesize a Petri net to exhibit the desired behavior specified as a partial language. We next discuss the solvability of this problem and last present the cutline of a solution technique.