PCHECK: A Delay Analysis Tool for High Performance LSI Design
Summary :
This paper describes new problems in delay analysis for high-performance LSI design and presents a static delay analysis tool PCHECK. PCHECK is characterized by (1) a new critical path trace algorithm for avoiding the error caused by signal transient time and (2) a precise delay calculation model for resistive shielding. Experimental results show that the delay calculation error in the worst case is less than 20 ps.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E79-A No.12 pp.2117-2122
- Publication Date
- 1996/12/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
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Yoshio MIKI, "PCHECK: A Delay Analysis Tool for High Performance LSI Design" in IEICE TRANSACTIONS on Fundamentals,
vol. E79-A, no. 12, pp. 2117-2122, December 1996, doi: .
Abstract: This paper describes new problems in delay analysis for high-performance LSI design and presents a static delay analysis tool PCHECK. PCHECK is characterized by (1) a new critical path trace algorithm for avoiding the error caused by signal transient time and (2) a precise delay calculation model for resistive shielding. Experimental results show that the delay calculation error in the worst case is less than 20 ps.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e79-a_12_2117/_p
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@ARTICLE{e79-a_12_2117,
author={Yoshio MIKI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={PCHECK: A Delay Analysis Tool for High Performance LSI Design},
year={1996},
volume={E79-A},
number={12},
pages={2117-2122},
abstract={This paper describes new problems in delay analysis for high-performance LSI design and presents a static delay analysis tool PCHECK. PCHECK is characterized by (1) a new critical path trace algorithm for avoiding the error caused by signal transient time and (2) a precise delay calculation model for resistive shielding. Experimental results show that the delay calculation error in the worst case is less than 20 ps.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - PCHECK: A Delay Analysis Tool for High Performance LSI Design
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2117
EP - 2122
AU - Yoshio MIKI
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E79-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 1996
AB - This paper describes new problems in delay analysis for high-performance LSI design and presents a static delay analysis tool PCHECK. PCHECK is characterized by (1) a new critical path trace algorithm for avoiding the error caused by signal transient time and (2) a precise delay calculation model for resistive shielding. Experimental results show that the delay calculation error in the worst case is less than 20 ps.
ER -
English
