This paper aims to establish expressions for IEEE 802.11 string-topology multi-hop networks with transmission control protocol (TCP) traffic flow. The relationship between the throughput and transport-layer function in string-topology multi-hop network is investigated. From the investigations, we obtain an analysis policy that the TCP throughput under the TCP functions is obtained by deriving the throughput of the network with simplified into two asymmetric user datagram protocol flows. To express the asymmetry, analytical expressions in medium access control-, network-, and transport layers are obtained based on the airtime expression. The expressions of the network layer and those of transport layer are linked using the “delayed ACK constraint,” which is a new concept for TCP analysis. The analytical predictions agree well with the simulation results, which prove the validity of the obtained analytical expressions and the analysis policy in this paper.

String-topology multi-hop network is often selected as an analysis object because it is one of the fundamental network topologies. The purpose of this paper is to establish expression for end-to-end delay for IEEE 802.11 string-topology multi-hop networks. For obtaining the analytical expression, the effects of frame collisions and carrier-sensing effect from other nodes under the non-saturated condition are obtained for each node in the network. For expressing the properties in non-saturated condition, a new parameter, which is frame-existence probability, is defined. The end-to-end delay of a string-topology multi-hop network can be derived as the sum of the transmission delays in the network flow. The analytical predictions agree with simulation results well, which show validity of the obtained analytical expressions.

We examine delay performance of packets from constant bit rate (CBR) traffic whose delay is affected by non-real-time traffic. The delay performance is analyzed by solving the Σ Di/G/1 queue with vacations. Our analysis allows heterogeneous service time and heterogeneous interarrival time. Thus, we can get the impact of packet length of a stream on the delay time of other streams. We then give various numerical results for enterprise multimedia networks, which include voice, video and data communication services. From our quantitative evaluation, we conclude that packet length of video traffic has large influence on the delay time of voice traffic while voice traffic gives a little impact on the delay time of video traffic.

Multi-cycle paths are paths between registers where 2 or more clock cycles are allowed to propagate signals, and the detection of multi-cycle paths is important in deciding proper clock period, timing verification and logic optimization. This paper presents a satisfiability-based multi-cycle path detection method, where the detection problems are reduced to CNF formulae and the satisfiability is checked using SAT provers. We also show heuristics on conversion from multi-level circuits into CNF formulae. We have applied our method to ISCAS'89 benchmarks and other sample circuits. Experimental results show the remarkable improvements on the size of manipulatable circuits.

In this paper, we discuss the access control in multimedia CDMA ALOHA protocol. We introduce a new algorithm for the access control based on Modified Channel Load Sensing Protocol (MCLSP) in an integrated voice and two different classes of data users, high bit rate and low bit rate, exist in a multi-code CDMA Slotted ALOHA system. With our new algorithm, we show that the throughput of high bit rate data users, as well as, the total throughput of the data medium can be optimized and take a maximum value even at high values of offered loads. We also investigate the performance when voice activity detection (VAD) is considered in voice transmission.

This paper introduces a new kind of false path, which is sensitizable but does not affect the decision of the maximum clock frequency. Such false paths exist in multi-clock operations controlled by waiting states, and the delay time of these paths can be greater than the clock period. This paper proposes a method to detect these waiting false paths based on the symbolic state traversal. In this method, the maximum allowable clock cycle of each path is computed using update cycles of each register.

This paper describes new problems in delay analysis for high-performance LSI design and presents a static delay analysis tool PCHECK. PCHECK is characterized by (1) a new critical path trace algorithm for avoiding the error caused by signal transient time and (2) a precise delay calculation model for resistive shielding. Experimental results show that the delay calculation error in the worst case is less than 20 ps.