IEICE TRANSACTIONS on Fundamentals
Timing Verification of Sequential Logic Circuits Based on Controlled Multi-Clock Path Analysis
Summary :
This paper introduces a new kind of false path, which is sensitizable but does not affect the decision of the maximum clock frequency. Such false paths exist in multi-clock operations controlled by waiting states, and the delay time of these paths can be greater than the clock period. This paper proposes a method to detect these waiting false paths based on the symbolic state traversal. In this method, the maximum allowable clock cycle of each path is computed using update cycles of each register.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E81-A No.12 pp.2515-2520
- Publication Date
- 1998/12/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Timing Verification and Optimization
Authors
Keyword
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Kazuhiro NAKAMURA, Shinji KIMURA, Kazuyoshi TAKAGI, Katsumasa WATANABE, "Timing Verification of Sequential Logic Circuits Based on Controlled Multi-Clock Path Analysis" in IEICE TRANSACTIONS on Fundamentals,
vol. E81-A, no. 12, pp. 2515-2520, December 1998, doi: .
Abstract: This paper introduces a new kind of false path, which is sensitizable but does not affect the decision of the maximum clock frequency. Such false paths exist in multi-clock operations controlled by waiting states, and the delay time of these paths can be greater than the clock period. This paper proposes a method to detect these waiting false paths based on the symbolic state traversal. In this method, the maximum allowable clock cycle of each path is computed using update cycles of each register.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e81-a_12_2515/_p
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@ARTICLE{e81-a_12_2515,
author={Kazuhiro NAKAMURA, Shinji KIMURA, Kazuyoshi TAKAGI, Katsumasa WATANABE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Timing Verification of Sequential Logic Circuits Based on Controlled Multi-Clock Path Analysis},
year={1998},
volume={E81-A},
number={12},
pages={2515-2520},
abstract={This paper introduces a new kind of false path, which is sensitizable but does not affect the decision of the maximum clock frequency. Such false paths exist in multi-clock operations controlled by waiting states, and the delay time of these paths can be greater than the clock period. This paper proposes a method to detect these waiting false paths based on the symbolic state traversal. In this method, the maximum allowable clock cycle of each path is computed using update cycles of each register.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - Timing Verification of Sequential Logic Circuits Based on Controlled Multi-Clock Path Analysis
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2515
EP - 2520
AU - Kazuhiro NAKAMURA
AU - Shinji KIMURA
AU - Kazuyoshi TAKAGI
AU - Katsumasa WATANABE
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E81-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 1998
AB - This paper introduces a new kind of false path, which is sensitizable but does not affect the decision of the maximum clock frequency. Such false paths exist in multi-clock operations controlled by waiting states, and the delay time of these paths can be greater than the clock period. This paper proposes a method to detect these waiting false paths based on the symbolic state traversal. In this method, the maximum allowable clock cycle of each path is computed using update cycles of each register.
ER -
English
