This paper describes a top-down floorplanning scheme for VLSI chips which is constructed on the basis of a heuristic algorithm and an interactive placement improvement process in conjunction with a knowledge-based expert systems approach. This scheme determines not only relative positions of the modules to be mounted on a chip but also shapes and areas of modules, according to specifications imposed on the total chip area, aspect ratios of modules, wire lengths of specific nets, electrical performances, and so forth. Several implementation results are also shown to reveal the performance of this scheme.