A Spread-Spectrum Clock Generator Using Fractional-N PLL with an Extended Range ΣΔ Modulator

Yi-Bin HSIEH; Yao-Huang KAO

doi:10.1093/ietele/e89-c.6.851

A Spread-Spectrum Clock Generator Using Fractional-N PLL with an Extended Range ΣΔ Modulator

Yi-Bin HSIEH, Yao-Huang KAO

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A spread-spectrum clock generator (SSCG) using fractional-N phase-locked loop (PLL) with an extended range sigma-delta (ΣΔ) modulator is presented in this paper. The proposed ΣΔ modulator simply adds an extra output bit in the first stage modulator. It can enlarge the input range about three times as compared to the conventional modulator and solve the saturation problem when the input exceeds the boundary of the conventional modulator. A flexible digital modulation controller can generate center and down spread-spectrum modulation and each has spread ratios of 0.4%, 0.8%, 1.6% and 3.2%. The proposed SSCG has been fabricated in TSMC 0.35-µm double-poly quadruple-metal CMOS process with output frequency of 300 MHz. The active area is 0.630.62 mm² and the power consumption is 17.5 mW.

Publication: IEICE TRANSACTIONS on Electronics Vol.E89-C No.6 pp.851-857

Publication Date: 2006/06/01

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Online ISSN: 1745-1353

DOI: 10.1093/ietele/e89-c.6.851

Type of Manuscript: PAPER

Category: Integrated Electronics

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Yi-Bin HSIEH, Yao-Huang KAO, "A Spread-Spectrum Clock Generator Using Fractional-N PLL with an Extended Range ΣΔ Modulator" in IEICE TRANSACTIONS on Electronics, vol. E89-C, no. 6, pp. 851-857, June 2006, doi: 10.1093/ietele/e89-c.6.851.
Abstract: A spread-spectrum clock generator (SSCG) using fractional-N phase-locked loop (PLL) with an extended range sigma-delta (ΣΔ) modulator is presented in this paper. The proposed ΣΔ modulator simply adds an extra output bit in the first stage modulator. It can enlarge the input range about three times as compared to the conventional modulator and solve the saturation problem when the input exceeds the boundary of the conventional modulator. A flexible digital modulation controller can generate center and down spread-spectrum modulation and each has spread ratios of 0.4%, 0.8%, 1.6% and 3.2%. The proposed SSCG has been fabricated in TSMC 0.35-µm double-poly quadruple-metal CMOS process with output frequency of 300 MHz. The active area is 0.630.62 mm² and the power consumption is 17.5 mW.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e89-c.6.851/_p

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@ARTICLE{e89-c_6_851,
author={Yi-Bin HSIEH, Yao-Huang KAO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Spread-Spectrum Clock Generator Using Fractional-N PLL with an Extended Range ΣΔ Modulator},
year={2006},
volume={E89-C},
number={6},
pages={851-857},
abstract={A spread-spectrum clock generator (SSCG) using fractional-N phase-locked loop (PLL) with an extended range sigma-delta (ΣΔ) modulator is presented in this paper. The proposed ΣΔ modulator simply adds an extra output bit in the first stage modulator. It can enlarge the input range about three times as compared to the conventional modulator and solve the saturation problem when the input exceeds the boundary of the conventional modulator. A flexible digital modulation controller can generate center and down spread-spectrum modulation and each has spread ratios of 0.4%, 0.8%, 1.6% and 3.2%. The proposed SSCG has been fabricated in TSMC 0.35-µm double-poly quadruple-metal CMOS process with output frequency of 300 MHz. The active area is 0.630.62 mm² and the power consumption is 17.5 mW.},
keywords={},
doi={10.1093/ietele/e89-c.6.851},
ISSN={1745-1353},
month={June},}

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TY - JOUR
TI - A Spread-Spectrum Clock Generator Using Fractional-N PLL with an Extended Range ΣΔ Modulator
T2 - IEICE TRANSACTIONS on Electronics
SP - 851
EP - 857
AU - Yi-Bin HSIEH
AU - Yao-Huang KAO
PY - 2006
DO - 10.1093/ietele/e89-c.6.851
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E89-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2006
AB - A spread-spectrum clock generator (SSCG) using fractional-N phase-locked loop (PLL) with an extended range sigma-delta (ΣΔ) modulator is presented in this paper. The proposed ΣΔ modulator simply adds an extra output bit in the first stage modulator. It can enlarge the input range about three times as compared to the conventional modulator and solve the saturation problem when the input exceeds the boundary of the conventional modulator. A flexible digital modulation controller can generate center and down spread-spectrum modulation and each has spread ratios of 0.4%, 0.8%, 1.6% and 3.2%. The proposed SSCG has been fabricated in TSMC 0.35-µm double-poly quadruple-metal CMOS process with output frequency of 300 MHz. The active area is 0.630.62 mm² and the power consumption is 17.5 mW.
ER -