Simultaneous Compensation of RC Mismatch and Clock Skew in Time-Interleaved S/H Circuits
Summary :
The RC mismatch among S/H stages for time-interleaved ADCs causes a phase error and a gain error and the phase error is dominant. The paper points out that clock skew and the phase error caused by the RC mismatch have similar effects on the sampling error and then can be compensated with the clock skew compensation. Simulation results agree well with the theoretical analysis. With the phase error compensation of RC mismatch, the SNDR in 14b ADC can be improved by more than 15 dB in the case that the bandwidth of S/H circuits is 3 times the sampling frequency. This paper also proposes a method of clock skew and RC mismatch compensation in time-interleaved sample-and-hold (S/H) circuits by sampling clock phase adjusting.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E89-C No.6 pp.710-716
- Publication Date
- 2006/06/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e89-c.6.710
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
- Category
Authors
Keyword
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Zheng LIU, Masanori FURUTA, Shoji KAWAHITO, "Simultaneous Compensation of RC Mismatch and Clock Skew in Time-Interleaved S/H Circuits" in IEICE TRANSACTIONS on Electronics,
vol. E89-C, no. 6, pp. 710-716, June 2006, doi: 10.1093/ietele/e89-c.6.710.
Abstract: The RC mismatch among S/H stages for time-interleaved ADCs causes a phase error and a gain error and the phase error is dominant. The paper points out that clock skew and the phase error caused by the RC mismatch have similar effects on the sampling error and then can be compensated with the clock skew compensation. Simulation results agree well with the theoretical analysis. With the phase error compensation of RC mismatch, the SNDR in 14b ADC can be improved by more than 15 dB in the case that the bandwidth of S/H circuits is 3 times the sampling frequency. This paper also proposes a method of clock skew and RC mismatch compensation in time-interleaved sample-and-hold (S/H) circuits by sampling clock phase adjusting.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e89-c.6.710/_p
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@ARTICLE{e89-c_6_710,
author={Zheng LIU, Masanori FURUTA, Shoji KAWAHITO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Simultaneous Compensation of RC Mismatch and Clock Skew in Time-Interleaved S/H Circuits},
year={2006},
volume={E89-C},
number={6},
pages={710-716},
abstract={The RC mismatch among S/H stages for time-interleaved ADCs causes a phase error and a gain error and the phase error is dominant. The paper points out that clock skew and the phase error caused by the RC mismatch have similar effects on the sampling error and then can be compensated with the clock skew compensation. Simulation results agree well with the theoretical analysis. With the phase error compensation of RC mismatch, the SNDR in 14b ADC can be improved by more than 15 dB in the case that the bandwidth of S/H circuits is 3 times the sampling frequency. This paper also proposes a method of clock skew and RC mismatch compensation in time-interleaved sample-and-hold (S/H) circuits by sampling clock phase adjusting.},
keywords={},
doi={10.1093/ietele/e89-c.6.710},
ISSN={1745-1353},
month={June},}
Copy
TY - JOUR
TI - Simultaneous Compensation of RC Mismatch and Clock Skew in Time-Interleaved S/H Circuits
T2 - IEICE TRANSACTIONS on Electronics
SP - 710
EP - 716
AU - Zheng LIU
AU - Masanori FURUTA
AU - Shoji KAWAHITO
PY - 2006
DO - 10.1093/ietele/e89-c.6.710
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E89-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2006
AB - The RC mismatch among S/H stages for time-interleaved ADCs causes a phase error and a gain error and the phase error is dominant. The paper points out that clock skew and the phase error caused by the RC mismatch have similar effects on the sampling error and then can be compensated with the clock skew compensation. Simulation results agree well with the theoretical analysis. With the phase error compensation of RC mismatch, the SNDR in 14b ADC can be improved by more than 15 dB in the case that the bandwidth of S/H circuits is 3 times the sampling frequency. This paper also proposes a method of clock skew and RC mismatch compensation in time-interleaved sample-and-hold (S/H) circuits by sampling clock phase adjusting.
ER -
English
