A 32-bit embedded RISC microcontroller core targeted for automotive, industrial, and PC-peripheral applications has been developed to offer the smaller code size, lower-latency instruction and interrupt processing needed for next-generation microcontrollers. The 360 MIPS/400MFLOPS/200 MHz core--based on the Harvard bus architecture--uses 0.13/0.15-µm CMOS technology and consists of a CPU, FPU, and register banks. To reduce the size of the control programs, new instructions have been added to the instruction set. These new instructions, as well as an enhanced C compiler, produce object files about 25% smaller than those for a previous designed core. A dual-issue superscalar structure consisting of three- or five-stage pipelines provides instruction processing with low latency. The cycle performance is thus an average of 1.8 times faster than the previous designed core. The superscalar structure is used to save 19 CPU registers in parallel when executing interrupt processing. That is, it saves the 19 CPU registers to the resister bank by accessing four registers at a time. This structure significantly improves interrupt response time from 37 cycles to 6 cycles.
Yasuo SUGURE
Seiji TAKEUCHI
Yuichi ABE
Hiromichi YAMADA
Kazuya HIRAYANAGI
Akihiko TOMITA
Kesami HAGIWARA
Takeshi KATAOKA
Takanori SHIMURA
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Yasuo SUGURE, Seiji TAKEUCHI, Yuichi ABE, Hiromichi YAMADA, Kazuya HIRAYANAGI, Akihiko TOMITA, Kesami HAGIWARA, Takeshi KATAOKA, Takanori SHIMURA, "Low-Latency Superscalar and Small-Code-Size Microcontroller Core for Automotive, Industrial, and PC-Peripheral Applications" in IEICE TRANSACTIONS on Electronics,
vol. E89-C, no. 6, pp. 844-850, June 2006, doi: 10.1093/ietele/e89-c.6.844.
Abstract: A 32-bit embedded RISC microcontroller core targeted for automotive, industrial, and PC-peripheral applications has been developed to offer the smaller code size, lower-latency instruction and interrupt processing needed for next-generation microcontrollers. The 360 MIPS/400MFLOPS/200 MHz core--based on the Harvard bus architecture--uses 0.13/0.15-µm CMOS technology and consists of a CPU, FPU, and register banks. To reduce the size of the control programs, new instructions have been added to the instruction set. These new instructions, as well as an enhanced C compiler, produce object files about 25% smaller than those for a previous designed core. A dual-issue superscalar structure consisting of three- or five-stage pipelines provides instruction processing with low latency. The cycle performance is thus an average of 1.8 times faster than the previous designed core. The superscalar structure is used to save 19 CPU registers in parallel when executing interrupt processing. That is, it saves the 19 CPU registers to the resister bank by accessing four registers at a time. This structure significantly improves interrupt response time from 37 cycles to 6 cycles.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e89-c.6.844/_p
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@ARTICLE{e89-c_6_844,
author={Yasuo SUGURE, Seiji TAKEUCHI, Yuichi ABE, Hiromichi YAMADA, Kazuya HIRAYANAGI, Akihiko TOMITA, Kesami HAGIWARA, Takeshi KATAOKA, Takanori SHIMURA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Low-Latency Superscalar and Small-Code-Size Microcontroller Core for Automotive, Industrial, and PC-Peripheral Applications},
year={2006},
volume={E89-C},
number={6},
pages={844-850},
abstract={A 32-bit embedded RISC microcontroller core targeted for automotive, industrial, and PC-peripheral applications has been developed to offer the smaller code size, lower-latency instruction and interrupt processing needed for next-generation microcontrollers. The 360 MIPS/400MFLOPS/200 MHz core--based on the Harvard bus architecture--uses 0.13/0.15-µm CMOS technology and consists of a CPU, FPU, and register banks. To reduce the size of the control programs, new instructions have been added to the instruction set. These new instructions, as well as an enhanced C compiler, produce object files about 25% smaller than those for a previous designed core. A dual-issue superscalar structure consisting of three- or five-stage pipelines provides instruction processing with low latency. The cycle performance is thus an average of 1.8 times faster than the previous designed core. The superscalar structure is used to save 19 CPU registers in parallel when executing interrupt processing. That is, it saves the 19 CPU registers to the resister bank by accessing four registers at a time. This structure significantly improves interrupt response time from 37 cycles to 6 cycles.},
keywords={},
doi={10.1093/ietele/e89-c.6.844},
ISSN={1745-1353},
month={June},}
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TY - JOUR
TI - Low-Latency Superscalar and Small-Code-Size Microcontroller Core for Automotive, Industrial, and PC-Peripheral Applications
T2 - IEICE TRANSACTIONS on Electronics
SP - 844
EP - 850
AU - Yasuo SUGURE
AU - Seiji TAKEUCHI
AU - Yuichi ABE
AU - Hiromichi YAMADA
AU - Kazuya HIRAYANAGI
AU - Akihiko TOMITA
AU - Kesami HAGIWARA
AU - Takeshi KATAOKA
AU - Takanori SHIMURA
PY - 2006
DO - 10.1093/ietele/e89-c.6.844
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E89-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2006
AB - A 32-bit embedded RISC microcontroller core targeted for automotive, industrial, and PC-peripheral applications has been developed to offer the smaller code size, lower-latency instruction and interrupt processing needed for next-generation microcontrollers. The 360 MIPS/400MFLOPS/200 MHz core--based on the Harvard bus architecture--uses 0.13/0.15-µm CMOS technology and consists of a CPU, FPU, and register banks. To reduce the size of the control programs, new instructions have been added to the instruction set. These new instructions, as well as an enhanced C compiler, produce object files about 25% smaller than those for a previous designed core. A dual-issue superscalar structure consisting of three- or five-stage pipelines provides instruction processing with low latency. The cycle performance is thus an average of 1.8 times faster than the previous designed core. The superscalar structure is used to save 19 CPU registers in parallel when executing interrupt processing. That is, it saves the 19 CPU registers to the resister bank by accessing four registers at a time. This structure significantly improves interrupt response time from 37 cycles to 6 cycles.
ER -