Sleep transistors such as MTCMOS and SCCMOS drastically reduce leakage current, but their ON resistances cause significant performance degradation. Larger sleep transistors reduce their ON resistances, but increase leakage current in a sleep mode. Decoupling capacitors beside sleep transistors reduce leakage current. Experimental results show that PMOS SCCMOS with a 4 pF decoupling capacitor reduces leakage current by 1/673 on a 64 bit adder in a 90 nm process.

This paper proposes an instruction-level power estimation method for an embedded RISC processor, the power consumption of which fluctuates so much by applications and input data. The proposed method estimates the power consumption from the result of ISS (Instruction Set Simulator) and energy tables according to Hamming Distance of Registers (HDR) of all instructions. It is over 105 times faster than the gate-level detailed logic simulation, while the estimated power curves have the same tendency with those from the logic simulation. The proposed method realizes both accurate and fast power estimation of embedded processors.