The increasing demand for millimeter-wave (mmWave) frequencies with wider signal bandwidths, such as 5G NR, requires large investments on test equipment. This work presents a 5G mmWave up/down-converter with a 40 GHz LO, fabricated in custom PCBs with off-the-shelf components. The mmWave converter has broad IF and RF bandwidths of 1∼5 GHz and 21∼45 GHz, and the built-in LO generates 20∼29.5 GHz and 33.5∼40 GHz of output. To achieve high linearity of the converter simultaneously, the LO must produce low-phase-noise and be capable of high harmonics/spur rejection, and design techniques related to these features are demonstrated. Additionally, a reconfigurable IF amplifier for bi-directional conversion is included and demonstrates low gain variation to maintain the linearity of the wideband modulation signals. The final designed converter is tested with 5G OFDM 64-QAM 100 MHz 1-CC (4-CC) signals and shows RF/IF output power of -3/8 dBm with a linear range of 35 (30)/38 (33) dB at an EVM of 25 dB.

In general, since the in-band noise of phase-locked loops (PLLs) is mainly caused by charge pumps (CPs), large-size transistors that occupy a large area are used to improve in-band noise of CPs. With the high demand for low phase noise in recent high-performance communication systems, the issue of the trade-off between occupied area and noise in conventional CPs has become significant. A noise-canceling CP circuit is presented in this paper to mitigate the trade-off between occupied area and noise. The proposed CP can achieve lower noise performance than conventional CPs by performing additional noise cancelation. According to the simulation results, the proposed CP can reduce the current noise to 57% with the same occupied area, or can reduce the occupied area to 22% compared with that of the conventional CPs at the same noise performance. We fabricated a prototype of the proposed CP embedded in a 28-GHz LC-PLL using a 16-nm FinFET process, and 1.2-dB improvement in single sideband integrated phase noise is achieved.

A 19.1-to-20.4 GHz sigma-delta fractional-N frequency synthesizer with two-point modulation (TPM) for frequency modulated continuous wave (FMCW) radar applications is presented. The FMCW synthesizer proposes a digital and voltage controlled oscillator (D/VCO) with large continuous frequency tuning range and small digital controlled oscillator (DCO) gain variation to support TPM. By using TPM technique, it avoids the correlation between loop bandwidth and chirp slope, which is beneficial to fast chirp, phase noise and linearity. The start frequency, bandwidth and slope of the FMCW signal are all reconfigurable independently. The FMCW synthesizer achieves a measured phase noise of -93.32 dBc/Hz at 1MHz offset from a 19.25 GHz carrier and less than 10 µs locking time. The root-mean-square (RMS) frequency error is only 112 kHz with 94 kHz/µs chirp slope, and 761 kHz with a fast slope of 9.725 MHz/µs respectively. Implemented in 65 nm CMOS process, the synthesizer consumes 74.3 mW with output buffer.

This paper presents a 27.5-29.6GHz fractional-N frequency synthesizer using reference and frequency doublers to achieve low in-band and out-of-band phase-noise for 5G mobile communications. A consideration of the baseband carrier recovery circuit helps estimate phase noise requirement for high modulation scheme. The push-push amplifier and 28GHz balun help achieving differential signals with low out-of-band phase noise while consuming low power. A charge pump with gated offset as well as reference doubler help reducing PD noise resulting in low in-band phase noise while sampling loop filter helps reduce spurs. The proposed synthesizer has been implemented in 65nm CMOS technology achieving an in-band and out-of-band phase noise of -78dBc/Hz and -126dBc/Hz, respectively. It consumes only a total power of 33mW. The jitter-power figure-of-merit (FOM) is -231dB which is the highest among the state of the art >20GHz fractional-N PLLs using a low reference clock (<200MHz). The measured reference spurs are less than -80dBc.

This paper introduces a novel Direct Digital Frequency Synthesizer based on Complementary Dual-Phase Latch-Based sequencing method. Compared to conventional Direct Digital Frequency Synthesizer using Flip-Flop as synchronizing element, the proposed architecture allows to double the data sampling rate while trading-off area and Power Efficiency. Digital domain modulations can be easily implemented by using a Direct Digital Frequency Synthesizer. However, due to performance limitations, CMOS-based applications have been almost exclusively restricted to VHF, UHF and L bands. This work aims to increase the operation speed and extend the applicability of this technology to Multi-band Multi-standard wireless systems operating up to 2.7 GHz. The design features a 24 bits pipelined Phase Accumulator and a 14x10 bits Phase to Amplitude Converter. The Phase to Amplitude Converter module is compressed by using Quarter Wave Symmetry technique and is entirely made up of combinational logic inserted into 12 Complementary Dual-Phase Latch-Based pipeline stages. The logic is represented in the form of Sum of Product terms obtained from a 14x10 bits sinusoidal Look-Up-Table. The proposed Direct Digital Frequency Synthesizer is designed and simulated based on 65nm CMOS standard-cell technology. A maximum data sampling rate of 6.8 GS/s is expected. Estimated Spurious Free Dynamic Range and Power Efficiency are 61 dBc and 22 mW/(GS/s) respectively.

An on-chip monitoring circuit using a sub-sampling scheme, which consists of a 6-bit flash analog-to-digital converter (ADC) and a 51-phase phase-locked loop (PLL)-based frequency synthesizer, is proposed to analyze the signal integrity of a single-ended 8-Gb/s octal data rate (ODR) chip-to-chip interface with a source synchronous clocking scheme.

This work presents a novel counter-based randomization method for use in a flying-adder frequency synthesizer with a cost-effective structure that can replace the fractional accumulator. The proposed technique involves a counter, a comparator and a modified linear feedback shift register. The power consumption and speed bottleneck of the conventional flying-adder are significantly reduced. The modified linear shift feedback register is used as a pseudo random data generator, suppressing the spurious tones arise from the periodic carry sequences that is generated by the fractional accumulator. Furthermore, the proposed counter-based randomization method greatly reduces the large memory size that is required by the conventional approach to carry randomization. A test chip for the proposed counter-based randomization method is fabricated in the TSMC 0.18,$mu $m 1P6M CMOS process, with the core area of 0.093,mm$^{mathrm{2}}$. The output frequency had a range of 43.4,MHz, extasciitilde 225.8,MHz at 1.8,V with peak-to-peak jitter (Pk-Pk) jitter 139.2,ps at 225.8,MHz. Power consumption is 2.8,mW @ 225.8,MHz with 1.8 supply voltage.

A monolithic frequency synthesizer with wide tuning range, low phase noise and spurs was realized in 0.13,$mu$m CMOS technology. It consists of an analog PLL, a harmonic-rejection mixer and injection-locked frequency doublers to cover the whole 6--18,GHz frequency range. To achieve a low phase noise performance, a sub-sampling PLL with non-dividers was employed. The synthesizer can achieve phase noise $-$113.7,dBc/Hz@100,kHz in the best case and the reference spur is below $-$60,dBc. The core of the synthesizer consumes about 110,mA*1.2,V.

We propose a methodology of loop design optimization for fourth-order fractional-N phase locked loop (PLL) frequency synthesizers featuring a short settling time of 5 µsec for applications in an active RFID (radio frequency identification) and automobile smart-key systems. To establish the optimized design flow, equations presenting the relationship between the specification and PLL loop parameters in terms of settling time, loop bandwidth, phase margin, and phase noise are summarized. The proposed design flow overcomes the settling time inaccuracy in conventional second-order approximation methods by obtaining the accurate relationship between settling time and loop bandwidth with the MATLAB Control System Toolbox for the fourth-order PLLs. The proposed flow also features the worst-case design by taking account of the process, voltage, and temperature (PVT) variations in loop filter components, and considers the tradeoff between phase noise and area. The three-step optimization process consists of 1) the derivation of the accurate relationship between the settling time and loop bandwidth for various PVT conditions, 2) the derivation of phase noise and area as functions of area-dominant filter capacitance, and 3) the derivation of all PLL loop components values. The optimized design result is compared with circuit simulations using an actually designed fourth-order fractional-N PLL in a 1.8 V 0.18 µm CMOS technology. The error between the design and simulation for the setting time is reduced from 0.63 µsec in the second-order approximation to 0.23 µsec in the fourth-order optimization that proves the validity of the proposed method for the high-speed settling operations.

This paper shows a new pulse swallow programmable frequency divider with the division step size of 0.5. To realize the division step size of 0.5 by a conventional pulse swallow method, we propose a parallel dual modulus prescaler with the division ratio of P and P + 0.5. It consists of simple circuit elements and has an advantage over the conventional dual modulus prescaler with the division step size of 0.5 in high frequency operation. The proposed parallel dual modulus prescaler with the division ratio 8 and 8.5 is implemented in the 0.13-µm CMOS technology. The proposed architecture achieves 7 times higher frequency operation than the conventional one theoretically. It is verified the functions over 5 GHz.

In this letter, an improved triple-tunable frequency synthesizer structure to achieve both high frequency resolution and fast switching speed without degradation of spurious signals (spurs) level performance is proposed. According to this structure, a high performance millimeter-wave frequency synthesizer with low spurious, low phase noise, and fast switching speed, is developed. This synthesizer driven by the direct digital synthesizer (DDS) AD9956 can adjust the output of a DDS and frequency division ratios of two variable frequency dividers (VFDs) to move the spurious components outside the loop bandwidth of the phase-locked loop (PLL). Moreover, the ADF4252 based microwave PLL can further suppress the phase noise. Experimental results from the implemented synthesizer show that remarkable performance improvements have been achieved.

This paper proposes a new sine wave approximation method for the PAC of DDFS. Sine wave is approximated by removing the harmonic components from trapezoid waveform. Experimental results show that the proposed PAC is advantageous in the SFDR range less than 60 dBc due to its small hardware cost.

A 1.8 V, 5 GHz low power frequency synthesizer for Wireless Sensor Networks is presented in 0.18 µm CMOS technology. A low power phase-switching prescaler is designed, and the current mode phase rotator is merged into the first divide-by-2 circuit of the prescaler to reduce power and propagation delay. An improved charge pump circuit is proposed to compensate for the dynamic effects with the charge pump. By a divide-by-2 circuit, the frequency synthesizer can provide a 2.324-2.714 GHz quadrature output frequency in 1 MHz steps with a 4 MHz reference frequency. The measured output phase noise is -110 dBc/Hz at 1-MHz offset frequency. The power consumption of the PLL is 11.2 mW at 1.8 V supply voltage.

The increasing demand of low power Direct Digital Frequency Synthesizer (DDFS) leads to the requirement of efficient compression methods to reduce ROM size for storing sine function values. This paper presents a technique to achieve very high compression ratio by using the optimized four-segment linear difference method. The proposed technique results in the ROM compression ratio of about 117.3:1 and the word size reduction of 6 bits for the design of a DDFS with 11-bit sine amplitude output. This high compression ratio result is very promising to meet the requirement of low power consumption and low hardware complexity in digital VLSI technology.

AC-waveform synthesis with quantum-mechanical accuracy has been attracting many researchers, especially metrologists in national metrology institutes, not only for its scientific interest but its potential benefit to industries. We describe the current status at National Metrology Institute of Japan of development of a Josephson arbitrary waveform synthesizer based on programmable and pulse-driven Josephson junction arrays.

The multistage noise-shaping (MASH) delta-sigma modulator (DSM) is the key element in a fractional-N frequency synthesizer. A hardware simplification method with subtraction inversion is proposed for delta-path's design in a MASH delta-sigma modulator. The subtraction inversion method focuses on simplification of adder-subtractor unit in the delta path with inversion of subtraction signal. It achieves with less hardware cost as compared with the conventional approaches. As a result, the hardware organization is regular and easy for expanding into higher order MASH DSM design. Analytical details of the implementation way and hardware cost function with N-th order configuration are presented. Finally, simulations with hardware description language as well as synthesis data verified the proposed design method.

This paper presents a novel spur suppression technique using a three-phase holding pulse for a direct digital synthesizer (DDS) with a two-phase holding digital-to-analog converter (2PH-DAC). A 2PH-DAC, which uses a reverse-sign step-function as a sampling pulse waveform instead of a commonly-used gate function of zeroth-order hold, enhances the first image of aliasing, which is of higher frequency than the fundamental. Therefore, the first image can be treated as a desired signal, while the fundamental and the second image are spurs for a DDS with a 2PH-DAC (2PH-DDS). The main problem of the 2PH-DDS is close spurs in the case that signal frequency is near Nyquist frequency or sampling frequency. This paper proposes a novel spur suppression technique for a 2PH-DDS. A configuration of a 2PH-DDS is first explained, and spectral properties are analyzed. Based on the analysis, a technique using a three-phase holding pulse to cancel spurs is proposed. Evaluated spur levels of the proposed synthesizer are from -51 to -34 dBc, and are improved by 25 dB or more by the proposed technique.

This paper presents a wide range DCO with fine discrete tuning steps using a ΣΔ modulation technique for UWB frequency synthesizer. The proposed discrete tuning scheme provides a low effective frequency resolution without any degradation of the phase noise performance. With its three step discrete tunings, the DCO simultaneously has a wide tuning range and fine tuning steps. The frequency synthesizer was implemented using 0.13 µm CMOS technology. The tuning range of the DCO is 5.8-6.8 GHz with an effective frequency resolution of 3.9 kHz. It achieves a measured phase noise of -108 dBc/Hz at 1 MHz offset and a tuning range of 16.8% with the power consumption of 5.9 mW. The figure of merit with the tuning range is -181.5 dBc/Hz.

A 60-GHz phase-locked loop (PLL) with an inductor-less prescaler is fabricated in a 90-nm CMOS process. The inductor-less prescaler has a smaller chip area than previously reported ones. The PLL operates from 61 to 63 GHz and consumes 78 mW from a 1.2 V supply. The phase noise at 100 kHz and 1 MHz offset from carrier are -72 and -80 dBc/Hz, respectively. The prescaler occupies 8040 µm2. The active area of the PLL is 0.31 mm2.

This paper analyzes the spurious sources in DDS synthesizers and deduces the simple model of DDS output signal. The method of feeding pseudo-random noise into the phase accumulator for spurious reduction is discussed. A new method for spurious reduction by compensating for DAC integer nonlinearity is proposed with two DACs and a power combiner. One DAC generates the error signal to compensate for the other DAC INL. The factor how the amplitude error and the phase error between the two combined signals affect the spurious level is also analyzed. The experiment shows that the spurious reduction can be improved by at least 18 dB, which proves the validity of the DAC INL compensation method for the spurious reduction.