IEICE TRANSACTIONS on Fundamentals
An Improved Linear Difference Method with High ROM Compression Ratio in Direct Digital Frequency Synthesizer
Summary :
The increasing demand of low power Direct Digital Frequency Synthesizer (DDFS) leads to the requirement of efficient compression methods to reduce ROM size for storing sine function values. This paper presents a technique to achieve very high compression ratio by using the optimized four-segment linear difference method. The proposed technique results in the ROM compression ratio of about 117.3:1 and the word size reduction of 6 bits for the design of a DDFS with 11-bit sine amplitude output. This high compression ratio result is very promising to meet the requirement of low power consumption and low hardware complexity in digital VLSI technology.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E94-A No.3 pp.995-998
- Publication Date
- 2011/03/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E94.A.995
- Type of Manuscript
- LETTER
- Category
- Digital Signal Processing
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Keyword
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Van-Phuc HOANG, Cong-Kha PHAM, "An Improved Linear Difference Method with High ROM Compression Ratio in Direct Digital Frequency Synthesizer" in IEICE TRANSACTIONS on Fundamentals,
vol. E94-A, no. 3, pp. 995-998, March 2011, doi: 10.1587/transfun.E94.A.995.
Abstract: The increasing demand of low power Direct Digital Frequency Synthesizer (DDFS) leads to the requirement of efficient compression methods to reduce ROM size for storing sine function values. This paper presents a technique to achieve very high compression ratio by using the optimized four-segment linear difference method. The proposed technique results in the ROM compression ratio of about 117.3:1 and the word size reduction of 6 bits for the design of a DDFS with 11-bit sine amplitude output. This high compression ratio result is very promising to meet the requirement of low power consumption and low hardware complexity in digital VLSI technology.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E94.A.995/_p
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@ARTICLE{e94-a_3_995,
author={Van-Phuc HOANG, Cong-Kha PHAM, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An Improved Linear Difference Method with High ROM Compression Ratio in Direct Digital Frequency Synthesizer},
year={2011},
volume={E94-A},
number={3},
pages={995-998},
abstract={The increasing demand of low power Direct Digital Frequency Synthesizer (DDFS) leads to the requirement of efficient compression methods to reduce ROM size for storing sine function values. This paper presents a technique to achieve very high compression ratio by using the optimized four-segment linear difference method. The proposed technique results in the ROM compression ratio of about 117.3:1 and the word size reduction of 6 bits for the design of a DDFS with 11-bit sine amplitude output. This high compression ratio result is very promising to meet the requirement of low power consumption and low hardware complexity in digital VLSI technology.},
keywords={},
doi={10.1587/transfun.E94.A.995},
ISSN={1745-1337},
month={March},}
Copy
TY - JOUR
TI - An Improved Linear Difference Method with High ROM Compression Ratio in Direct Digital Frequency Synthesizer
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 995
EP - 998
AU - Van-Phuc HOANG
AU - Cong-Kha PHAM
PY - 2011
DO - 10.1587/transfun.E94.A.995
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E94-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2011
AB - The increasing demand of low power Direct Digital Frequency Synthesizer (DDFS) leads to the requirement of efficient compression methods to reduce ROM size for storing sine function values. This paper presents a technique to achieve very high compression ratio by using the optimized four-segment linear difference method. The proposed technique results in the ROM compression ratio of about 117.3:1 and the word size reduction of 6 bits for the design of a DDFS with 11-bit sine amplitude output. This high compression ratio result is very promising to meet the requirement of low power consumption and low hardware complexity in digital VLSI technology.
ER -
English
