The multistage noise-shaping (MASH) delta-sigma modulator (DSM) is the key element in a fractional-N frequency synthesizer. A hardware simplification method with subtraction inversion is proposed for delta-path's design in a MASH delta-sigma modulator. The subtraction inversion method focuses on simplification of adder-subtractor unit in the delta path with inversion of subtraction signal. It achieves with less hardware cost as compared with the conventional approaches. As a result, the hardware organization is regular and easy for expanding into higher order MASH DSM design. Analytical details of the implementation way and hardware cost function with N-th order configuration are presented. Finally, simulations with hardware description language as well as synthesis data verified the proposed design method.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copy
Pao-Lung CHEN, "Subtraction Inversion for Delta Path's Hardware Simplification in MASH Delta-Sigma Modulator" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 12, pp. 2616-2620, December 2010, doi: 10.1587/transfun.E93.A.2616.
Abstract: The multistage noise-shaping (MASH) delta-sigma modulator (DSM) is the key element in a fractional-N frequency synthesizer. A hardware simplification method with subtraction inversion is proposed for delta-path's design in a MASH delta-sigma modulator. The subtraction inversion method focuses on simplification of adder-subtractor unit in the delta path with inversion of subtraction signal. It achieves with less hardware cost as compared with the conventional approaches. As a result, the hardware organization is regular and easy for expanding into higher order MASH DSM design. Analytical details of the implementation way and hardware cost function with N-th order configuration are presented. Finally, simulations with hardware description language as well as synthesis data verified the proposed design method.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.2616/_p
Copy
@ARTICLE{e93-a_12_2616,
author={Pao-Lung CHEN, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Subtraction Inversion for Delta Path's Hardware Simplification in MASH Delta-Sigma Modulator},
year={2010},
volume={E93-A},
number={12},
pages={2616-2620},
abstract={The multistage noise-shaping (MASH) delta-sigma modulator (DSM) is the key element in a fractional-N frequency synthesizer. A hardware simplification method with subtraction inversion is proposed for delta-path's design in a MASH delta-sigma modulator. The subtraction inversion method focuses on simplification of adder-subtractor unit in the delta path with inversion of subtraction signal. It achieves with less hardware cost as compared with the conventional approaches. As a result, the hardware organization is regular and easy for expanding into higher order MASH DSM design. Analytical details of the implementation way and hardware cost function with N-th order configuration are presented. Finally, simulations with hardware description language as well as synthesis data verified the proposed design method.},
keywords={},
doi={10.1587/transfun.E93.A.2616},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Subtraction Inversion for Delta Path's Hardware Simplification in MASH Delta-Sigma Modulator
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2616
EP - 2620
AU - Pao-Lung CHEN
PY - 2010
DO - 10.1587/transfun.E93.A.2616
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2010
AB - The multistage noise-shaping (MASH) delta-sigma modulator (DSM) is the key element in a fractional-N frequency synthesizer. A hardware simplification method with subtraction inversion is proposed for delta-path's design in a MASH delta-sigma modulator. The subtraction inversion method focuses on simplification of adder-subtractor unit in the delta path with inversion of subtraction signal. It achieves with less hardware cost as compared with the conventional approaches. As a result, the hardware organization is regular and easy for expanding into higher order MASH DSM design. Analytical details of the implementation way and hardware cost function with N-th order configuration are presented. Finally, simulations with hardware description language as well as synthesis data verified the proposed design method.
ER -