IEICE TRANSACTIONS on Electronics
A Time-Domain Architecture and Design Method of High Speed A-to-D Converters with Standard Cells
Summary :
In this paper, we describe a new method to deal with analog signal in time domain. The method converts voltage signal to time-interleaved phase modulation signal of clock edge. After being amplified by a new time amplifier (TA), phases of the signal are converted to digital codes by successive approximation time-to-digital converter (SA-TDC). The test chip includes 8 interleaved 4 bit SA-TDCs with short latency. The chip operates up to 4.4 GHz. The measured ENOB is 3.51 bit and FOM is 0.49 pJ/conv.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E96-C No.6 pp.813-819
- Publication Date
- 2013/06/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E96.C.813
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
- Category
Authors
Masao TAKAYAMA
Matsushita Electric Industrial Co., Ltd.
Shiro DOSHO
Matsushita Electric Industrial Co., Ltd.
Noriaki TAKEDA
Matsushita Electric Industrial Co., Ltd.
Masaya MIYAHARA
Tokyo Institute of Technology
Akira MATSUZAWA
Tokyo Institute of Technology
Keyword
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Masao TAKAYAMA, Shiro DOSHO, Noriaki TAKEDA, Masaya MIYAHARA, Akira MATSUZAWA, "A Time-Domain Architecture and Design Method of High Speed A-to-D Converters with Standard Cells" in IEICE TRANSACTIONS on Electronics,
vol. E96-C, no. 6, pp. 813-819, June 2013, doi: 10.1587/transele.E96.C.813.
Abstract: In this paper, we describe a new method to deal with analog signal in time domain. The method converts voltage signal to time-interleaved phase modulation signal of clock edge. After being amplified by a new time amplifier (TA), phases of the signal are converted to digital codes by successive approximation time-to-digital converter (SA-TDC). The test chip includes 8 interleaved 4 bit SA-TDCs with short latency. The chip operates up to 4.4 GHz. The measured ENOB is 3.51 bit and FOM is 0.49 pJ/conv.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E96.C.813/_p
Copy
@ARTICLE{e96-c_6_813,
author={Masao TAKAYAMA, Shiro DOSHO, Noriaki TAKEDA, Masaya MIYAHARA, Akira MATSUZAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Time-Domain Architecture and Design Method of High Speed A-to-D Converters with Standard Cells},
year={2013},
volume={E96-C},
number={6},
pages={813-819},
abstract={In this paper, we describe a new method to deal with analog signal in time domain. The method converts voltage signal to time-interleaved phase modulation signal of clock edge. After being amplified by a new time amplifier (TA), phases of the signal are converted to digital codes by successive approximation time-to-digital converter (SA-TDC). The test chip includes 8 interleaved 4 bit SA-TDCs with short latency. The chip operates up to 4.4 GHz. The measured ENOB is 3.51 bit and FOM is 0.49 pJ/conv.},
keywords={},
doi={10.1587/transele.E96.C.813},
ISSN={1745-1353},
month={June},}
Copy
TY - JOUR
TI - A Time-Domain Architecture and Design Method of High Speed A-to-D Converters with Standard Cells
T2 - IEICE TRANSACTIONS on Electronics
SP - 813
EP - 819
AU - Masao TAKAYAMA
AU - Shiro DOSHO
AU - Noriaki TAKEDA
AU - Masaya MIYAHARA
AU - Akira MATSUZAWA
PY - 2013
DO - 10.1587/transele.E96.C.813
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E96-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2013
AB - In this paper, we describe a new method to deal with analog signal in time domain. The method converts voltage signal to time-interleaved phase modulation signal of clock edge. After being amplified by a new time amplifier (TA), phases of the signal are converted to digital codes by successive approximation time-to-digital converter (SA-TDC). The test chip includes 8 interleaved 4 bit SA-TDCs with short latency. The chip operates up to 4.4 GHz. The measured ENOB is 3.51 bit and FOM is 0.49 pJ/conv.
ER -
English
