IEICE TRANSACTIONS on Fundamentals
A Nonlinear Oscillator Network for Gray-Level Image Segmentation and PWM/PPM Circuits for Its VLSI Implementation
Summary :
This paper proposes a nonlinear oscillator network model for gray-level image segmentation suitable for massively parallel VLSI implementation. The model performs image segmentation in parallel using nonlinear analog dynamics. Because of the limited calculation precision in VLSI implementation, it is important to estimate the calculation precision required for proper operation. By numerical simulation, the necessary precision is estimated to be 5 bits. We propose a nonlinear oscillator network circuit using the pulse modulation approach suitable for an analog-digital merged circuit architecture. The basic operations of the nonlinear oscillator circuit and the connection weight circuit are confirmed by SPICE circuit simulation. The circuit simulation results also demonstrate that image segmentation can be performed within the order of 100 µs.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E83-A No.2 pp.329-336
- Publication Date
- 2000/02/25
- Publicized
- Online ISSN
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- Type of Manuscript
- Special Section PAPER (Special Section on Intelligent Signal and Image Processing)
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Hiroshi ANDO, Takashi MORIE, Makoto NAGATA, Atsushi IWATA, "A Nonlinear Oscillator Network for Gray-Level Image Segmentation and PWM/PPM Circuits for Its VLSI Implementation" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 2, pp. 329-336, February 2000, doi: .
Abstract: This paper proposes a nonlinear oscillator network model for gray-level image segmentation suitable for massively parallel VLSI implementation. The model performs image segmentation in parallel using nonlinear analog dynamics. Because of the limited calculation precision in VLSI implementation, it is important to estimate the calculation precision required for proper operation. By numerical simulation, the necessary precision is estimated to be 5 bits. We propose a nonlinear oscillator network circuit using the pulse modulation approach suitable for an analog-digital merged circuit architecture. The basic operations of the nonlinear oscillator circuit and the connection weight circuit are confirmed by SPICE circuit simulation. The circuit simulation results also demonstrate that image segmentation can be performed within the order of 100 µs.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_2_329/_p
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@ARTICLE{e83-a_2_329,
author={Hiroshi ANDO, Takashi MORIE, Makoto NAGATA, Atsushi IWATA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Nonlinear Oscillator Network for Gray-Level Image Segmentation and PWM/PPM Circuits for Its VLSI Implementation},
year={2000},
volume={E83-A},
number={2},
pages={329-336},
abstract={This paper proposes a nonlinear oscillator network model for gray-level image segmentation suitable for massively parallel VLSI implementation. The model performs image segmentation in parallel using nonlinear analog dynamics. Because of the limited calculation precision in VLSI implementation, it is important to estimate the calculation precision required for proper operation. By numerical simulation, the necessary precision is estimated to be 5 bits. We propose a nonlinear oscillator network circuit using the pulse modulation approach suitable for an analog-digital merged circuit architecture. The basic operations of the nonlinear oscillator circuit and the connection weight circuit are confirmed by SPICE circuit simulation. The circuit simulation results also demonstrate that image segmentation can be performed within the order of 100 µs.},
keywords={},
doi={},
ISSN={},
month={February},}
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TY - JOUR
TI - A Nonlinear Oscillator Network for Gray-Level Image Segmentation and PWM/PPM Circuits for Its VLSI Implementation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 329
EP - 336
AU - Hiroshi ANDO
AU - Takashi MORIE
AU - Makoto NAGATA
AU - Atsushi IWATA
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2000
AB - This paper proposes a nonlinear oscillator network model for gray-level image segmentation suitable for massively parallel VLSI implementation. The model performs image segmentation in parallel using nonlinear analog dynamics. Because of the limited calculation precision in VLSI implementation, it is important to estimate the calculation precision required for proper operation. By numerical simulation, the necessary precision is estimated to be 5 bits. We propose a nonlinear oscillator network circuit using the pulse modulation approach suitable for an analog-digital merged circuit architecture. The basic operations of the nonlinear oscillator circuit and the connection weight circuit are confirmed by SPICE circuit simulation. The circuit simulation results also demonstrate that image segmentation can be performed within the order of 100 µs.
ER -
English
