IEICE TRANSACTIONS on Fundamentals
A CMOS Spiking Neural Network Circuit with Symmetric/Asymmetric STDP Function
Summary :
In this paper, we propose an analog CMOS circuit which achieves spiking neural networks with spike-timing dependent synaptic plasticity (STDP). In particular, we propose a STDP circuit with symmetric function for the first time, and also we demonstrate associative memory operation in a Hopfield-type feedback network with STDP learning. In our spiking neuron model, analog information expressing processing results is given by the relative timing of spike firing events. It is well known that a biological neuron changes its synaptic weights by STDP, which provides learning rules depending on relative timing between asynchronous spikes. Therefore, STDP can be used for spiking neural systems with learning function. The measurement results of fabricated chips using TSMC 0.25 µm CMOS process technology demonstrate that our spiking neuron circuit can construct feedback networks and update synaptic weights based on relative timing between asynchronous spikes by a symmetric or an asymmetric STDP circuits.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E92-A No.7 pp.1690-1698
- Publication Date
- 2009/07/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E92.A.1690
- Type of Manuscript
- PAPER
- Category
- Neural Networks and Bioengineering
Authors
Keyword
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Hideki TANAKA, Takashi MORIE, Kazuyuki AIHARA, "A CMOS Spiking Neural Network Circuit with Symmetric/Asymmetric STDP Function" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 7, pp. 1690-1698, July 2009, doi: 10.1587/transfun.E92.A.1690.
Abstract: In this paper, we propose an analog CMOS circuit which achieves spiking neural networks with spike-timing dependent synaptic plasticity (STDP). In particular, we propose a STDP circuit with symmetric function for the first time, and also we demonstrate associative memory operation in a Hopfield-type feedback network with STDP learning. In our spiking neuron model, analog information expressing processing results is given by the relative timing of spike firing events. It is well known that a biological neuron changes its synaptic weights by STDP, which provides learning rules depending on relative timing between asynchronous spikes. Therefore, STDP can be used for spiking neural systems with learning function. The measurement results of fabricated chips using TSMC 0.25 µm CMOS process technology demonstrate that our spiking neuron circuit can construct feedback networks and update synaptic weights based on relative timing between asynchronous spikes by a symmetric or an asymmetric STDP circuits.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.1690/_p
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@ARTICLE{e92-a_7_1690,
author={Hideki TANAKA, Takashi MORIE, Kazuyuki AIHARA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A CMOS Spiking Neural Network Circuit with Symmetric/Asymmetric STDP Function},
year={2009},
volume={E92-A},
number={7},
pages={1690-1698},
abstract={In this paper, we propose an analog CMOS circuit which achieves spiking neural networks with spike-timing dependent synaptic plasticity (STDP). In particular, we propose a STDP circuit with symmetric function for the first time, and also we demonstrate associative memory operation in a Hopfield-type feedback network with STDP learning. In our spiking neuron model, analog information expressing processing results is given by the relative timing of spike firing events. It is well known that a biological neuron changes its synaptic weights by STDP, which provides learning rules depending on relative timing between asynchronous spikes. Therefore, STDP can be used for spiking neural systems with learning function. The measurement results of fabricated chips using TSMC 0.25 µm CMOS process technology demonstrate that our spiking neuron circuit can construct feedback networks and update synaptic weights based on relative timing between asynchronous spikes by a symmetric or an asymmetric STDP circuits.},
keywords={},
doi={10.1587/transfun.E92.A.1690},
ISSN={1745-1337},
month={July},}
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TY - JOUR
TI - A CMOS Spiking Neural Network Circuit with Symmetric/Asymmetric STDP Function
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1690
EP - 1698
AU - Hideki TANAKA
AU - Takashi MORIE
AU - Kazuyuki AIHARA
PY - 2009
DO - 10.1587/transfun.E92.A.1690
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2009
AB - In this paper, we propose an analog CMOS circuit which achieves spiking neural networks with spike-timing dependent synaptic plasticity (STDP). In particular, we propose a STDP circuit with symmetric function for the first time, and also we demonstrate associative memory operation in a Hopfield-type feedback network with STDP learning. In our spiking neuron model, analog information expressing processing results is given by the relative timing of spike firing events. It is well known that a biological neuron changes its synaptic weights by STDP, which provides learning rules depending on relative timing between asynchronous spikes. Therefore, STDP can be used for spiking neural systems with learning function. The measurement results of fabricated chips using TSMC 0.25 µm CMOS process technology demonstrate that our spiking neuron circuit can construct feedback networks and update synaptic weights based on relative timing between asynchronous spikes by a symmetric or an asymmetric STDP circuits.
ER -
English
