A generalized version of a piece-wise constant (ab. PWC) spiking neuron model is presented. It is shown that the generalization enables the model to reproduce 20 activities in the Izhikevich model. Among the activities, we analyze tonic bursting. Using an analytical one-dimensional iterative map, it is shown that the model can reproduce a burst-related bifurcation scenario, which is qualitatively similar to that of the Izhikevich model. The bifurcation scenario can be observed in an actual hardware.

An asynchronous sequential logic spiking neuron is an artificial neuron model that can exhibit various bifurcations and nonlinear responses to stimulation inputs. In this paper, a pulse-coupled system of the asynchronous sequential logic spiking neurons is presented. Numerical simulations show that the coupled system can exhibit various lockings and related nonlinear responses. Then, theoretical sufficient parameter conditions for existence of typical lockings are provided. Usefulness of the parameter conditions is validated by comparing with the numerical simulation results as well as field programmable gate array experiment results.

In this paper, an artificial sub-threshold oscillating spiking neuron is presented and its response phenomena to an input spike-train are analyzed. In addition, a dynamic parameter update rule of the neuron for achieving synchronizations to the input spike-train having various spike frequencies is presented. Using an analytical two-dimensional return map, local stability of the parameter update rule is analyzed. Furthermore, a pulse-coupled network of the neurons is presented and its basic self-organizing function is analyzed. Fundamental comparisons are also presented.

In this paper, we propose an analog CMOS circuit which achieves spiking neural networks with spike-timing dependent synaptic plasticity (STDP). In particular, we propose a STDP circuit with symmetric function for the first time, and also we demonstrate associative memory operation in a Hopfield-type feedback network with STDP learning. In our spiking neuron model, analog information expressing processing results is given by the relative timing of spike firing events. It is well known that a biological neuron changes its synaptic weights by STDP, which provides learning rules depending on relative timing between asynchronous spikes. Therefore, STDP can be used for spiking neural systems with learning function. The measurement results of fabricated chips using TSMC 0.25 µm CMOS process technology demonstrate that our spiking neuron circuit can construct feedback networks and update synaptic weights based on relative timing between asynchronous spikes by a symmetric or an asymmetric STDP circuits.

An integrate-and-fire-type spiking feedback network is discussed in this paper. In our spiking neuron model, analog information expressing processing results is given by the relative relation of spike firing. Therefore, for spiking feedback networks, all neurons should fire (pseudo-)periodically. However, an integrate-and-fire-type neuron generates no spike unless its internal potential exceeds the threshold. To solve this problem, we propose negative thresholding operation. In this paper, this operation is achieved by a global excitatory unit. This unit operates immediately after receiving the first spike input. We have designed a CMOS spiking feedback network VLSI circuit with the global excitatory unit for Hopfield-type associative memory. The circuit simulation results show that the network achieves correct association operation.

This article theoretically provides the ensemble average and the ensemble variance of membrane potential of an integrate-and-fire neuron, when the neuron receives random spikes from the other neurons. The model assumes that EPSPs rise and fall continuously. Our theoretical result shows good agreement with a numerical simulation.