IEICE TRANSACTIONS on Electronics
A Fully Integrated 6.25% Pull-in Range Digital PLL for ISDN Primary Rate Interface LSI
Summary :
A fully integrated digital PLL (Phase Locked Loop) with on-chip CMOS oscillator is described. Nominal division number of the variable divider is automatically tuned in this digital PLL and this feature makes it possible to widen the pull-in range. In general, output jitter may increase if the pull-in range is widened. To overcome this problem, output jitter is reduced by utilizing the dual loop architecture. Wide pull-in range enables us on-chip oscillator, which is not so precise as the expensive crystal oscillator. This CMOS oscillator must be carefully designed to be stable against the temperature and the supply voltage variations. Using these digital PLL techniques, together with the on-chip CMOS oscillator, a fully integrated PLL can be achieved. Circuits are designed for 1.544 Mbit/s ISDN primary rate interface, and 6.25% pull-in range is obtained.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E75-C No.3 pp.280-287
- Publication Date
- 1992/03/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Analog LSI and Related Technology)
- Category
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Harufusa KONDOH, Seiji KOZAKI, Shinya MAKINO, Hiromi NOTANI, Fuminobu HIDANI, Masao NAKAYA, "A Fully Integrated 6.25% Pull-in Range Digital PLL for ISDN Primary Rate Interface LSI" in IEICE TRANSACTIONS on Electronics,
vol. E75-C, no. 3, pp. 280-287, March 1992, doi: .
Abstract: A fully integrated digital PLL (Phase Locked Loop) with on-chip CMOS oscillator is described. Nominal division number of the variable divider is automatically tuned in this digital PLL and this feature makes it possible to widen the pull-in range. In general, output jitter may increase if the pull-in range is widened. To overcome this problem, output jitter is reduced by utilizing the dual loop architecture. Wide pull-in range enables us on-chip oscillator, which is not so precise as the expensive crystal oscillator. This CMOS oscillator must be carefully designed to be stable against the temperature and the supply voltage variations. Using these digital PLL techniques, together with the on-chip CMOS oscillator, a fully integrated PLL can be achieved. Circuits are designed for 1.544 Mbit/s ISDN primary rate interface, and 6.25% pull-in range is obtained.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e75-c_3_280/_p
Copy
@ARTICLE{e75-c_3_280,
author={Harufusa KONDOH, Seiji KOZAKI, Shinya MAKINO, Hiromi NOTANI, Fuminobu HIDANI, Masao NAKAYA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Fully Integrated 6.25% Pull-in Range Digital PLL for ISDN Primary Rate Interface LSI},
year={1992},
volume={E75-C},
number={3},
pages={280-287},
abstract={A fully integrated digital PLL (Phase Locked Loop) with on-chip CMOS oscillator is described. Nominal division number of the variable divider is automatically tuned in this digital PLL and this feature makes it possible to widen the pull-in range. In general, output jitter may increase if the pull-in range is widened. To overcome this problem, output jitter is reduced by utilizing the dual loop architecture. Wide pull-in range enables us on-chip oscillator, which is not so precise as the expensive crystal oscillator. This CMOS oscillator must be carefully designed to be stable against the temperature and the supply voltage variations. Using these digital PLL techniques, together with the on-chip CMOS oscillator, a fully integrated PLL can be achieved. Circuits are designed for 1.544 Mbit/s ISDN primary rate interface, and 6.25% pull-in range is obtained.},
keywords={},
doi={},
ISSN={},
month={March},}
Copy
TY - JOUR
TI - A Fully Integrated 6.25% Pull-in Range Digital PLL for ISDN Primary Rate Interface LSI
T2 - IEICE TRANSACTIONS on Electronics
SP - 280
EP - 287
AU - Harufusa KONDOH
AU - Seiji KOZAKI
AU - Shinya MAKINO
AU - Hiromi NOTANI
AU - Fuminobu HIDANI
AU - Masao NAKAYA
PY - 1992
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E75-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 1992
AB - A fully integrated digital PLL (Phase Locked Loop) with on-chip CMOS oscillator is described. Nominal division number of the variable divider is automatically tuned in this digital PLL and this feature makes it possible to widen the pull-in range. In general, output jitter may increase if the pull-in range is widened. To overcome this problem, output jitter is reduced by utilizing the dual loop architecture. Wide pull-in range enables us on-chip oscillator, which is not so precise as the expensive crystal oscillator. This CMOS oscillator must be carefully designed to be stable against the temperature and the supply voltage variations. Using these digital PLL techniques, together with the on-chip CMOS oscillator, a fully integrated PLL can be achieved. Circuits are designed for 1.544 Mbit/s ISDN primary rate interface, and 6.25% pull-in range is obtained.
ER -
English
