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[Author] Sy-Chyuan HWU(1hit)

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  • A Multi-Band Burst-Mode Clock and Data Recovery Circuit

    Che-Fu LIANG  Sy-Chyuan HWU  Shen-Iuan LIU  

     
    PAPER-Analog and Communications

      Vol:
    E90-C No:4
      Page(s):
    802-810

    A multi-band burst-mode clock and data recovery (BMCDR) circuit is presented. The available data rates are 2488.32 Mbps, 1244.16 Mbps, 622.08 Mbps, and 155.52 Mbps, which are specified in a gigabit-capable passive optical network (GPON) [1]. A half-rate and low-jitter gated voltage-controlled oscillator (GVCO) and a phase-controlled frequency divider are used to achieve the multi-band reception. The proposed BMCDR circuit has been fabricated in a 0.18 µm CMOS process. Its active area is 0.41 mm2 and consumes 70 mW including I/O buffers from a 1.8 V supply.