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This paper presents the implementation of a 3 V low power multi-rate of 156, 622, and 1244 Mbps clock and data recovery circuit (CDR) for optical communications tranceiver using new parallel clock recovery architecture based on dual charge-pump PLL. Designed circuit recovers eight-phase clock signals which are one-eighth frequency of the input signal. While the typical system uses the method that compares the input data with recovered clock, the proposed circuit compares a 1/2-bit delayed input data with the serial data generated by the recovered eight-phase clock signals. The advantage of the circuit is that the implementation is easy, since each sub blocks have one-eighth frequency of the input data signal. Morevover, since the circuit works at one-eighth frequency of the input data, it dissipates less power than conventional CMOS recovery circuit. Simulation results show that this recovery circuit can work with power dissipation of less than 40 mW with a single 3 V supply. All the simulations are based on HYUNDAI 0.65 µm N-Well CMOS double-poly double-metal technology.

- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E83-A No.8 pp.1720-1727

- Publication Date
- 2000/08/25

- Publicized

- Online ISSN

- DOI

- Type of Manuscript
- PAPER

- Category
- General Fundamentals and Boundaries

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Hae-Moon SEO, Chang-Gene WOO, Sang-Won OH, Sung-Wook JUNG, Pyung CHOI, "A 3 V Low Power 156/622/1244 Mbps CMOS Parallel Clock and Data Recovery Circuit for Optical Communications" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 8, pp. 1720-1727, August 2000, doi: .

Abstract: This paper presents the implementation of a 3 V low power multi-rate of 156, 622, and 1244 Mbps clock and data recovery circuit (CDR) for optical communications tranceiver using new parallel clock recovery architecture based on dual charge-pump PLL. Designed circuit recovers eight-phase clock signals which are one-eighth frequency of the input signal. While the typical system uses the method that compares the input data with recovered clock, the proposed circuit compares a 1/2-bit delayed input data with the serial data generated by the recovered eight-phase clock signals. The advantage of the circuit is that the implementation is easy, since each sub blocks have one-eighth frequency of the input data signal. Morevover, since the circuit works at one-eighth frequency of the input data, it dissipates less power than conventional CMOS recovery circuit. Simulation results show that this recovery circuit can work with power dissipation of less than 40 mW with a single 3 V supply. All the simulations are based on HYUNDAI 0.65 µm N-Well CMOS double-poly double-metal technology.

URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_8_1720/_p

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@ARTICLE{e83-a_8_1720,

author={Hae-Moon SEO, Chang-Gene WOO, Sang-Won OH, Sung-Wook JUNG, Pyung CHOI, },

journal={IEICE TRANSACTIONS on Fundamentals},

title={A 3 V Low Power 156/622/1244 Mbps CMOS Parallel Clock and Data Recovery Circuit for Optical Communications},

year={2000},

volume={E83-A},

number={8},

pages={1720-1727},

abstract={This paper presents the implementation of a 3 V low power multi-rate of 156, 622, and 1244 Mbps clock and data recovery circuit (CDR) for optical communications tranceiver using new parallel clock recovery architecture based on dual charge-pump PLL. Designed circuit recovers eight-phase clock signals which are one-eighth frequency of the input signal. While the typical system uses the method that compares the input data with recovered clock, the proposed circuit compares a 1/2-bit delayed input data with the serial data generated by the recovered eight-phase clock signals. The advantage of the circuit is that the implementation is easy, since each sub blocks have one-eighth frequency of the input data signal. Morevover, since the circuit works at one-eighth frequency of the input data, it dissipates less power than conventional CMOS recovery circuit. Simulation results show that this recovery circuit can work with power dissipation of less than 40 mW with a single 3 V supply. All the simulations are based on HYUNDAI 0.65 µm N-Well CMOS double-poly double-metal technology.},

keywords={},

doi={},

ISSN={},

month={August},}

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TY - JOUR

TI - A 3 V Low Power 156/622/1244 Mbps CMOS Parallel Clock and Data Recovery Circuit for Optical Communications

T2 - IEICE TRANSACTIONS on Fundamentals

SP - 1720

EP - 1727

AU - Hae-Moon SEO

AU - Chang-Gene WOO

AU - Sang-Won OH

AU - Sung-Wook JUNG

AU - Pyung CHOI

PY - 2000

DO -

JO - IEICE TRANSACTIONS on Fundamentals

SN -

VL - E83-A

IS - 8

JA - IEICE TRANSACTIONS on Fundamentals

Y1 - August 2000

AB - This paper presents the implementation of a 3 V low power multi-rate of 156, 622, and 1244 Mbps clock and data recovery circuit (CDR) for optical communications tranceiver using new parallel clock recovery architecture based on dual charge-pump PLL. Designed circuit recovers eight-phase clock signals which are one-eighth frequency of the input signal. While the typical system uses the method that compares the input data with recovered clock, the proposed circuit compares a 1/2-bit delayed input data with the serial data generated by the recovered eight-phase clock signals. The advantage of the circuit is that the implementation is easy, since each sub blocks have one-eighth frequency of the input data signal. Morevover, since the circuit works at one-eighth frequency of the input data, it dissipates less power than conventional CMOS recovery circuit. Simulation results show that this recovery circuit can work with power dissipation of less than 40 mW with a single 3 V supply. All the simulations are based on HYUNDAI 0.65 µm N-Well CMOS double-poly double-metal technology.

ER -