IEICE TRANSACTIONS on Fundamentals
Performance Estimation at Architecture Level for Embedded Systems
Summary :
This paper devises a sophisticated approach to the performance estimation of an embedded hardware-software codesign system at the architecture level, which intends to optimize the hardware-software configuration in terms of processing time, power dissipation, and hardware cost. A distinctive feature of this approach consists in constructing a performance estimation model proper to each component of an embedded system, such as CPU core, RAM/ROM, cache memory, and application-specific hardware, by taking account of not only the functional performance but also the data transfer. The proposed estimation schemes are incorporated into an existing instruction set simulator, so that the actual performance can be estimated accurately at the architecture level. The experimental results demonstrate that the performance estimation approach enables the precise design decision at the architecture level, which greatly contributes toward enhancing the design ability dedicatedly for mobile appliances.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E85-A No.12 pp.2636-2644
- Publication Date
- 2002/12/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Performance Estimation
Authors
Keyword
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Hiroshi MIZUNO, Hiroyuki KOBAYASHI, Takao ONOYE, Isao SHIRAKAWA, "Performance Estimation at Architecture Level for Embedded Systems" in IEICE TRANSACTIONS on Fundamentals,
vol. E85-A, no. 12, pp. 2636-2644, December 2002, doi: .
Abstract: This paper devises a sophisticated approach to the performance estimation of an embedded hardware-software codesign system at the architecture level, which intends to optimize the hardware-software configuration in terms of processing time, power dissipation, and hardware cost. A distinctive feature of this approach consists in constructing a performance estimation model proper to each component of an embedded system, such as CPU core, RAM/ROM, cache memory, and application-specific hardware, by taking account of not only the functional performance but also the data transfer. The proposed estimation schemes are incorporated into an existing instruction set simulator, so that the actual performance can be estimated accurately at the architecture level. The experimental results demonstrate that the performance estimation approach enables the precise design decision at the architecture level, which greatly contributes toward enhancing the design ability dedicatedly for mobile appliances.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_12_2636/_p
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@ARTICLE{e85-a_12_2636,
author={Hiroshi MIZUNO, Hiroyuki KOBAYASHI, Takao ONOYE, Isao SHIRAKAWA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Performance Estimation at Architecture Level for Embedded Systems},
year={2002},
volume={E85-A},
number={12},
pages={2636-2644},
abstract={This paper devises a sophisticated approach to the performance estimation of an embedded hardware-software codesign system at the architecture level, which intends to optimize the hardware-software configuration in terms of processing time, power dissipation, and hardware cost. A distinctive feature of this approach consists in constructing a performance estimation model proper to each component of an embedded system, such as CPU core, RAM/ROM, cache memory, and application-specific hardware, by taking account of not only the functional performance but also the data transfer. The proposed estimation schemes are incorporated into an existing instruction set simulator, so that the actual performance can be estimated accurately at the architecture level. The experimental results demonstrate that the performance estimation approach enables the precise design decision at the architecture level, which greatly contributes toward enhancing the design ability dedicatedly for mobile appliances.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - Performance Estimation at Architecture Level for Embedded Systems
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2636
EP - 2644
AU - Hiroshi MIZUNO
AU - Hiroyuki KOBAYASHI
AU - Takao ONOYE
AU - Isao SHIRAKAWA
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E85-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2002
AB - This paper devises a sophisticated approach to the performance estimation of an embedded hardware-software codesign system at the architecture level, which intends to optimize the hardware-software configuration in terms of processing time, power dissipation, and hardware cost. A distinctive feature of this approach consists in constructing a performance estimation model proper to each component of an embedded system, such as CPU core, RAM/ROM, cache memory, and application-specific hardware, by taking account of not only the functional performance but also the data transfer. The proposed estimation schemes are incorporated into an existing instruction set simulator, so that the actual performance can be estimated accurately at the architecture level. The experimental results demonstrate that the performance estimation approach enables the precise design decision at the architecture level, which greatly contributes toward enhancing the design ability dedicatedly for mobile appliances.
ER -
English
