A Full-CMOS Single Chip Bluetooth LSI with 1.5 MHz-IF Receiver and Direct Modulation Transmitter

Fumitoshi HATORI; Hiroki ISHIKURO; Mototsugu HAMADA; Ken-ichi AGAWA; Shouhei KOUSAI; Hiroyuki KOBAYASHI; Duc Minh NGUYEN

A Full-CMOS Single Chip Bluetooth LSI with 1.5 MHz-IF Receiver and Direct Modulation Transmitter

Fumitoshi HATORI, Hiroki ISHIKURO, Mototsugu HAMADA, Ken-ichi AGAWA, Shouhei KOUSAI, Hiroyuki KOBAYASHI, Duc Minh NGUYEN

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This paper describes a full-CMOS single-chip Bluetooth LSI fabricated using a 0.18 µm CMOS, triple-well, quad-metal technology. The chip integrates radio and baseband, which is compliant with Bluetooth Core Specification version 1.1. A direct modulation transmitter and a low-IF receiver architecture are employed for the low-power and low-cost implementation. To reduce the power consumption of the digital blocks, it uses a clock gating technique during the active modes and a power manager during the low power modes. The maximum power consumption is 75 mW for the transmission, 120 mW for the reception and 30 µW for the low power mode operation. These values are low enough for mobile applications. Sensitivity of -80 dBm has been achieved and the transmitter can deliver up to 4 dBm.

Publication: IEICE TRANSACTIONS on Electronics Vol.E87-C No.4 pp.556-562

Publication Date: 2004/04/01

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Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)

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Fumitoshi HATORI, Hiroki ISHIKURO, Mototsugu HAMADA, Ken-ichi AGAWA, Shouhei KOUSAI, Hiroyuki KOBAYASHI, Duc Minh NGUYEN, "A Full-CMOS Single Chip Bluetooth LSI with 1.5 MHz-IF Receiver and Direct Modulation Transmitter" in IEICE TRANSACTIONS on Electronics, vol. E87-C, no. 4, pp. 556-562, April 2004, doi: .
Abstract: This paper describes a full-CMOS single-chip Bluetooth LSI fabricated using a 0.18 µm CMOS, triple-well, quad-metal technology. The chip integrates radio and baseband, which is compliant with Bluetooth Core Specification version 1.1. A direct modulation transmitter and a low-IF receiver architecture are employed for the low-power and low-cost implementation. To reduce the power consumption of the digital blocks, it uses a clock gating technique during the active modes and a power manager during the low power modes. The maximum power consumption is 75 mW for the transmission, 120 mW for the reception and 30 µW for the low power mode operation. These values are low enough for mobile applications. Sensitivity of -80 dBm has been achieved and the transmitter can deliver up to 4 dBm.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e87-c_4_556/_p

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@ARTICLE{e87-c_4_556,
author={Fumitoshi HATORI, Hiroki ISHIKURO, Mototsugu HAMADA, Ken-ichi AGAWA, Shouhei KOUSAI, Hiroyuki KOBAYASHI, Duc Minh NGUYEN, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Full-CMOS Single Chip Bluetooth LSI with 1.5 MHz-IF Receiver and Direct Modulation Transmitter},
year={2004},
volume={E87-C},
number={4},
pages={556-562},
abstract={This paper describes a full-CMOS single-chip Bluetooth LSI fabricated using a 0.18 µm CMOS, triple-well, quad-metal technology. The chip integrates radio and baseband, which is compliant with Bluetooth Core Specification version 1.1. A direct modulation transmitter and a low-IF receiver architecture are employed for the low-power and low-cost implementation. To reduce the power consumption of the digital blocks, it uses a clock gating technique during the active modes and a power manager during the low power modes. The maximum power consumption is 75 mW for the transmission, 120 mW for the reception and 30 µW for the low power mode operation. These values are low enough for mobile applications. Sensitivity of -80 dBm has been achieved and the transmitter can deliver up to 4 dBm.},
keywords={},
doi={},
ISSN={},
month={April},}

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TY - JOUR
TI - A Full-CMOS Single Chip Bluetooth LSI with 1.5 MHz-IF Receiver and Direct Modulation Transmitter
T2 - IEICE TRANSACTIONS on Electronics
SP - 556
EP - 562
AU - Fumitoshi HATORI
AU - Hiroki ISHIKURO
AU - Mototsugu HAMADA
AU - Ken-ichi AGAWA
AU - Shouhei KOUSAI
AU - Hiroyuki KOBAYASHI
AU - Duc Minh NGUYEN
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E87-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2004
AB - This paper describes a full-CMOS single-chip Bluetooth LSI fabricated using a 0.18 µm CMOS, triple-well, quad-metal technology. The chip integrates radio and baseband, which is compliant with Bluetooth Core Specification version 1.1. A direct modulation transmitter and a low-IF receiver architecture are employed for the low-power and low-cost implementation. To reduce the power consumption of the digital blocks, it uses a clock gating technique during the active modes and a power manager during the low power modes. The maximum power consumption is 75 mW for the transmission, 120 mW for the reception and 30 µW for the low power mode operation. These values are low enough for mobile applications. Sensitivity of -80 dBm has been achieved and the transmitter can deliver up to 4 dBm.
ER -