This paper describes a high-speed multichip (3232 space-division) switching module for high-definition TV broadcasting and switching systems. This newly developed module employs new Si-bipolar SST switching LSIs and a multi-layer substrate with a polyimide dielectric and a fine pattern of copper conductors. This substrate contains matrix-shaped thin film registers for terminated transmission and a spiral via hole structure to increase fabrication reliability. The module has 50 ohm characteristic impedance transmission lines with a deviation of less than 2.5%. The multichip module can handle a signal speed of 1.8 Gb/s using 1 : 1 and 1 : n connections. This technology allows a dramatic reduction in module size to 1/20 of that possible with conventional surface-mounted techniques.

This paper describes a high-density, high-pin-count flexible SMD connector used for high-speed data buses between MCMs or daughter boards. This connector consists of a flexible film cable interconnection with accurately controlled characteristic impedance, and a contact housing composed of double-line contacts and SMD type leads. It has 98 contacts each with a pitch of 0.4 mm. The connector mounting area is 6 mm wide and 23 mm long. The flexible cable has a double-sided triple-parallel micro stripline structure with an insertion force of less than 2.9 kgf and characteristic impedance of 48 to 50 Ω. Insertion loss is -0.5 dB at 600 MHz and crosstalk noise is less than 110 mV at 250 ps rising time. This connector can be used for high-speed data transmission of up to 300 ps rising time.

Many studies of deep neural networks have reported inference accelerators for improved energy efficiency. We propose methods for further improving energy efficiency while maintaining recognition accuracy, which were developed by the co-design of a filter-by-filter quantization scheme with variable bit precision and a hardware architecture that fully supports it. Filter-wise quantization reduces the average bit precision of weights, so execution times and energy consumption for inference are reduced in proportion to the total number of computations multiplied by the average bit precision of weights. The hardware utilization is also improved by a bit-parallel architecture suitable for granularly quantized bit precision of weights. We implement the proposed architecture on an FPGA and demonstrate that the execution cycles are reduced to 1/5.3 for ResNet-50 on ImageNet in comparison with a conventional method, while maintaining recognition accuracy.

This paper describes an innovative heat-pipe cooling technology for asynchronous transfer mode (ATM) switching multichip modules (MCMs) operating with a throughput of 40 Gb/s. Although high-speed ATM link-wires are connected at the top surface of the MCMs, there is no room to cool the MCM by forced air convection, because power and the system clock signal are supplied by connectors on the rear and periphery of the MCM. We therefore chose to attach a cold-plate to the back of each MCM. The condenser part of the heat pipe, which is mounted behind the power supply printed circuit board, is cooled by low-velocity forced air. Total power dissipation is about 30 watts per MCM. With a 2 m/s foreced airflow, the sub-switching-element module (four MCMs) operates at a throughput of 80 Gb/s with a maximum junction temperature of less than 85. Measured thermal resistance between the switch LSI junction and air is about 6/W. This heat-pipe cooling system has a small system footprint, compact hardware, and good cooling capacity.

This paper describes a trial coaxial surface mounted connector for PGA-type high-speed multichip modules (MCM). An MCM connector is needed to ensure testability and connection reliability of MCMs mounted on a printed circuit board. Our connector consists of a coaxial elements, a common ground housing made of conductive resin, and a ground contact spring plate. It has 68 signal contacts. We investigated the performance of this connector by experiment and simulation. Its insertion force is only about 53 gf per signal pin. The characteristic impedance is from 45.6 Ω to 61.4 Ω. The average resistance between two contacts is 28 mΩ with a deviation of less than plus or minus 5 mΩ. The insertion is -0.4 dB at 1.0 GHz. Crosstalk noise is less than 1.2%. This prototype connector can transmit pulses of up to 1.2 Gb/s, showing that it is applicable to high-speed MCMs.