Physical-Weight-Based Measurement Methodology Suppressing Noise or Reducing Test Time for High-Resolution Low-Speed ADCs
Summary :
We propose a statistical processing method to reduce the time of chip test of high-resolution and low-speed analog-to-digital converters (ADCs). For this kinds of ADCs, due to the influence of noise, conventional histogram or momentum method suffers from long time to collect required data for averaging. The proposed method, based on physically weighing the ADC, intending to physical weights in ADC/DAC under test. It can suppress white noise to 1/22 than conventional method in a case of 10bit binary ADC. Or it can reduce test data to 1/8 or less, which directly means to reduce measuring time to 1/8 or less. In addition, it earns complete Integrated Non-Linearity (INL) and Differential Non-linearity (DNL) even missing codes happens due to less data points. In this report, we theoretically describe how to guarantee missing codes at lacked measured data points.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E100-C No.6 pp.576-583
- Publication Date
- 2017/06/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E100.C.576
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies)
- Category
Authors
Mitsutoshi SUGAWARA
Tokyo Institute of Technology
Zule XU
Tokyo University of Science
Akira MATSUZAWA
Tokyo Institute of Technology
Keyword
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Mitsutoshi SUGAWARA, Zule XU, Akira MATSUZAWA, "Physical-Weight-Based Measurement Methodology Suppressing Noise or Reducing Test Time for High-Resolution Low-Speed ADCs" in IEICE TRANSACTIONS on Electronics,
vol. E100-C, no. 6, pp. 576-583, June 2017, doi: 10.1587/transele.E100.C.576.
Abstract: We propose a statistical processing method to reduce the time of chip test of high-resolution and low-speed analog-to-digital converters (ADCs). For this kinds of ADCs, due to the influence of noise, conventional histogram or momentum method suffers from long time to collect required data for averaging. The proposed method, based on physically weighing the ADC, intending to physical weights in ADC/DAC under test. It can suppress white noise to 1/22 than conventional method in a case of 10bit binary ADC. Or it can reduce test data to 1/8 or less, which directly means to reduce measuring time to 1/8 or less. In addition, it earns complete Integrated Non-Linearity (INL) and Differential Non-linearity (DNL) even missing codes happens due to less data points. In this report, we theoretically describe how to guarantee missing codes at lacked measured data points.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E100.C.576/_p
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@ARTICLE{e100-c_6_576,
author={Mitsutoshi SUGAWARA, Zule XU, Akira MATSUZAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Physical-Weight-Based Measurement Methodology Suppressing Noise or Reducing Test Time for High-Resolution Low-Speed ADCs},
year={2017},
volume={E100-C},
number={6},
pages={576-583},
abstract={We propose a statistical processing method to reduce the time of chip test of high-resolution and low-speed analog-to-digital converters (ADCs). For this kinds of ADCs, due to the influence of noise, conventional histogram or momentum method suffers from long time to collect required data for averaging. The proposed method, based on physically weighing the ADC, intending to physical weights in ADC/DAC under test. It can suppress white noise to 1/22 than conventional method in a case of 10bit binary ADC. Or it can reduce test data to 1/8 or less, which directly means to reduce measuring time to 1/8 or less. In addition, it earns complete Integrated Non-Linearity (INL) and Differential Non-linearity (DNL) even missing codes happens due to less data points. In this report, we theoretically describe how to guarantee missing codes at lacked measured data points.},
keywords={},
doi={10.1587/transele.E100.C.576},
ISSN={1745-1353},
month={June},}
Copy
TY - JOUR
TI - Physical-Weight-Based Measurement Methodology Suppressing Noise or Reducing Test Time for High-Resolution Low-Speed ADCs
T2 - IEICE TRANSACTIONS on Electronics
SP - 576
EP - 583
AU - Mitsutoshi SUGAWARA
AU - Zule XU
AU - Akira MATSUZAWA
PY - 2017
DO - 10.1587/transele.E100.C.576
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E100-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2017
AB - We propose a statistical processing method to reduce the time of chip test of high-resolution and low-speed analog-to-digital converters (ADCs). For this kinds of ADCs, due to the influence of noise, conventional histogram or momentum method suffers from long time to collect required data for averaging. The proposed method, based on physically weighing the ADC, intending to physical weights in ADC/DAC under test. It can suppress white noise to 1/22 than conventional method in a case of 10bit binary ADC. Or it can reduce test data to 1/8 or less, which directly means to reduce measuring time to 1/8 or less. In addition, it earns complete Integrated Non-Linearity (INL) and Differential Non-linearity (DNL) even missing codes happens due to less data points. In this report, we theoretically describe how to guarantee missing codes at lacked measured data points.
ER -
English
