In order to realize an Internet-of-Things (IoT) with tiny sensors integrated in our buildings, our clothing, and the public spaces, battery lifetime and battery size remain major challenges. Power reduction in IoT sensor nodes is determined by both sleep mode as well as active mode contributions. A power state machine, at the system level, is the key to achieve ultra-low average power consumption by alternating the system between active and sleep modes efficiently. While, power consumption in the active mode remains dominant, other power contributions like for timekeeping in standby and sleep conditions are becoming important as well. For example, non-conventional critical blocks, such as crystal oscillator (XO) and resistor-capacitor oscillator (RCO) become more crucial during the design phase. Apart from power reduction, low-voltage operation will further extend the battery life. A 2.4GHz multi-standard radio is presented, as a test case, with an average power consumption in the µW range, and state-of-the-art performance across a voltage supply range from 1.2V to 0.9V.

This study focuses on the design of electrical stimulator for retinal prosthesis. The stimulator must be designed such that the occurrence of electrolysis or any irreversible process in the electrodes and flexible lead is prevented in order to achieve safe stimulation over long periods using the large number of electrodes. Some types of biphasic current pulse circuits, charge balance circuits, and AC power delivery circuits were developed to address this issue. Electronic circuitry must be introduced in the stimulator to achieve the large number of electrodes required to obtain high quality of vision. The concept of a smart electrode, in which a microchip is embedded inside an electrode, is presented for future retinal prostheses with over 1000 electrodes.

A novel spur cancelled clock generator (SCCG) capable of recovering RX sensitivity degradations caused by digital clocks in wireless SoCs is presented. Clock spurs that degrade RX sensitivities are canceled by applying the SCCG to digital circuits or ADCs. The SCCG is integrated into a Bluetooth Low Energy (BLE) SoC fabricated in a 65 nm CMOS process. A measured clock spur reduction of 34 dB and an RX sensitivity recovery of 5 dB are achieved by the proposed SCCG. The power consumption and occupied area of the SCCG is only 18 µW and 40 μm × 120 μm, respectively.

60GHz wireless communication requires analog baseband circuits having a bandwidth of about 1GHz. This paper presents a wide bandwidth current-mode low pass filter technique which involves current amplifiers, resistors and capacitors. The proposed current-mode filter is obtained by replacing an integrator employing an op-amp with another integrator employing a current amplifier. With the low input impedance current amplifier having little variation of the input impedance, the proposed filter is expected to improve linearity and power efficiency. The proposed current amplifier which employs super source follower topology with complementary input is suitable for the filter because of its class AB operation. Although simulation results shows the conventional current amplifier which employs super source follower topology without the complementary input has 12Ω variation and 30Ω input impedance, the proposed current amplifier has 1Ω variation and 21Ω input impedance. A fourth order 1GHz bandwidth filter which involves the proposed current amplifiers is designed in a 65nm CMOS technology. The filter can achieve IIP3 of 1.3dBV and noise of 0.6mVrms with power consumption of 13mW under supply voltage of 1.2V according to simulation results with layout parasitic extraction models. Active area of the filter is 380μm×170μm.

This paper presents a high resolution mixed-domain Delta-Sigma (ΔΣ) time-to-digital converter (TDC) which utilizes a charge pump as time-to-voltage converter, a low resolution SAR ADC as quantizer, and a pair of delay-line digital-to-time converters to form a negative feedback. By never resetting the sampling capacitor of the charge-pump, an integrator is realized and first order noise shaping can be achieved. However, since the integrating capacitor is never cleared, this circuit is prone to charge-sharing issue during input sampling which can degrade TDC's performance. To deal with this issue, a compensation circuit consists of another pair of sampling capacitors and charge-pumps with doubled current is proposed. This TDC is designed and simulated in 65 nm CMOS technology and can operate at 200 MHz sampling frequency. For 2.5 MHz bandwidth, simulation shows that this TDC achieves 66.4 dB SNDR and 295 fs_rms integrated noise for ±1 ns input range. The proposed TDC consumes 1.78 mW power that translates to FoM of 208 fJ/conv.

In this paper, a 500 MHz-BW -52.5 dB-THD Voltage-to-Time Converter (VTC) in 28 nm CMOS is presented. A two-step transition inverter raises the Voltage-to-Time (VT) conversion gain to 100 ps/V which is >10x higher than a conventional current-starved inverter. The number of required inverter stages is reduced to 4 from 64, resulting in 1/8 conversion latency and thus 13.2 dB THD suppression at a 500 MHz full Nyquist frequency. A feedback control of the bias voltage in the two-step transition inverter suppresses PVT variations in the VT conversion gain. A test-chip measurement successfully demonstrates -52.5 dB THD at 500 MHz input frequency without sampling-and-hold circuits. Effective VT conversion range over +/-64 ps time difference is measured with 1.2 Vpp differential input while keeping high linearity of less than +/-0.53 LSB INL/DNL, which results in 1 ps/LSB conversion linearity. The proposed VTC occupies 84 um² silicon area and consumes 0.18 mW at 1 GS/s.

This paper present a 20-GHz differential push-push voltage controlled oscillator (VCO) for 60-GHz frequency synthesizer. The 20-GHz VCO consists of a 10-GHz in-phase injection-coupled QVCO (IPIC-QVCO) with tail-filter and a differential output push-push doubler for 20-GHz output. The VCO fabricated in 65-nm CMOS technology, it achieves tuning range of 3 GHz from 17.5 GHz to 20.4 GHz with a phase noise of -113.8 dBc/Hz at 1 MHz offset. The core oscillator consumes up to 71 mW power and a FoM of -180.2 dBc/Hz is achieved.

We propose a statistical processing method to reduce the time of chip test of high-resolution and low-speed analog-to-digital converters (ADCs). For this kinds of ADCs, due to the influence of noise, conventional histogram or momentum method suffers from long time to collect required data for averaging. The proposed method, based on physically weighing the ADC, intending to physical weights in ADC/DAC under test. It can suppress white noise to 1/22 than conventional method in a case of 10bit binary ADC. Or it can reduce test data to 1/8 or less, which directly means to reduce measuring time to 1/8 or less. In addition, it earns complete Integrated Non-Linearity (INL) and Differential Non-linearity (DNL) even missing codes happens due to less data points. In this report, we theoretically describe how to guarantee missing codes at lacked measured data points.

This paper presents a thin, compact beacon transmitter operating without needing battery replacement by using a photovoltaic (PV) film harvester. The beacon is formed of a power-control circuit (PCC) that can monitor small amounts of power from the harvester and properly control mode switching at low-power consumption. This leads to the realization of a maintenance-free beacon requiring no battery replacement. The beacon prototype is 55×20×2 mm in size and has a PV cell of 3 cm². It allows a start-up operation from just 44-lux illuminance. The PV area required for the operation can be 1.7 times smaller than that of conventional beacons, thanks to the current saving with appropriate sequential control of the PCC. Since the beacon makes operation possible in emergency stairs, underground passages and other dark places, the application field for Internet of things (IoT) services can be expanded. Furthermore, a beacon equipped with a secondary battery (BSB: Beacon with Secondary Battery) can be configured by adding a charge-discharge power monitoring circuit. The BSB transmits an advertising packet during the daytime while charging surplus power, and works using the stored power during the night; this results in a continuous operation for one week with one transmission every 3 seconds even at 0-lux illuminance. Without developing a new radiofrequency chip or module, commercial low-power devices can be easily adjusted depending on the application by adding appropriate power-control circuits. We are convinced that this design scheme will be effective as a rapid design proposal for IoT services.

In this paper, we present sub-1-V CMOS-based electrophoresis method for small-form-factor biomolecule manipulation that is contained in a microchip. This is the first time this type of device has been presented in the literature. By combining CMOS technology with electroless gold plating, the electrode pitch can be reduced and the required input voltage can be decreased to less than 1 V. We fabricated the CMOS electrophoresis chip in a cost-competitive 0.6 µm standard CMOS process. A sample/hold circuit in each cell is used to generate a constant output from an analog input. After forming gold electrodes using an electroless gold plating technique, we were able to manipulate red food coloring with a 0-0.7 V input voltage range. The results shows that the proposed CMOS chip is effective for electrophoresis-based manipulation.

High-resolution bio-imaging is a key component for the advancement of life science. CMOS electronics is one of the promising candidates for emerging high-resolution devices because it offers nano-scale transistors. However, the resolution of the existing CMOS bio-imaging devices is several micrometers, which is insufficient for analyzing small objects such as bacteria and viruses. This paper presents the results of an analysis of the scalability of a current-mode analog-to-time converter (CMATC) to develop a high-resolution CMOS biosensor array. Simulations were performed using 0.6-µm, 0.25-µm, and 0.065-µm CMOS technology nodes. The Simulation results for the power consumption and resolution (cell size) showed that the CMATC has high-scalability and is a promising candidate to enable high-resolution CMOS bio-imaging.

CMOS amperometric sensors with a microelectrode array offer great potential for counting bacteria because of their low cost, compact size, and ease of use. This paper presents a current-integration-based CMOS amperometric sensor for high-sensitivity bacteria counting. It has a current integrator for noise reduction and reportedly the most large-scale microelectrode array (1024 × 1024). This proposed sensor can count the number of bacteria ranging from a single cell to approximately a million cells. A prototype chip was fabricated using two-poly three-metal (2P3M) 0.6-µm standard CMOS technology. A 7.6 × 7.1-mm² chip operates from a 5V supply at 1.9mA. In addition, by using the prototype chip, we performed electrochemical measurement and partial 2D imaging of silicone through constant potential amperometry. The measurement results indicate that the proposed sensor chip was able to accurately readout redox current from the 1024 × 1024 sensor array.

This study mainly involved examining a high-directivity radiation system with spherical dielectric resonator as pseudo multipole source. The method of spherical wave expansion is focused on wherein the plane wave that is infinitely spread can be radiated from or absorbed by multipoles at the origin. It is not possible to explain this phenomenon by Huygens' principle, which is a basic principle of aperture antenna theory. Thus, in the study, a high-directivity beam design is proposed by synthesizing spherical waves. The directivity of the synthesized spherical wave corresponds with the angular momentum and angle, which is an uncertainty relation different from that of the aperture source. The estimation of the effective aperture of the synthesized spherical wave indicates that the wave intrinsic source is assumed to exist at the surface of the cutoff region. Finally, the results reveal that a radiation system without a singular point can be composed using a spherical dielectric resonator. The study discusses the potential of a high-directivity radiation system constructed by a multi-mode degenerate spherical dielectric resonator as a pseudo multipole source.

This paper describes, for the first time, an experimental study on the layout design considerations of GaAs HBT MMIC switchable-amplifier-chain-based power amplifiers (SWPAs) for CDMA handsets. The transient response of the quiescent current and output power (P_out) in GaAs HBT power amplifiers that consist of a main chain and a sub-chain is often affected by a thermal coupling between power stages and their bias circuits in the same chain or a thermal coupling between power stages and/or their bias circuits in different chains. In particular, excessively strong thermal coupling inside the MMIC SWPA causes failure in 3GPP-compliant inner loop power control tests. An experimental study reveals that both the preheating in the main/sub-chains and appropriate thermal coupling inside the main chain are very effective in reducing the turn-on delay for the two-parallel-amplifier-chain topology; for example, i) the sub-power stage is arranged near the main power stage, ii) the sub-driver stage is placed near the main driver stage and iii) the main driver bias circuit is placed near the main power stage and the sub-power stage. The SWPA operating in Band 9 (1749.9 to 1784.9 MHz), which was designed and fabricated from the foregoing considerations, shows a remarkable improvement in the P_out turn-on delay: a reduced power level error of 0.74 dB from turn-off to turn-on in the sub-amplifier chain and a reduced power level error of over 0.30 dB from turn-off to turn-on in the main amplifier chain. The main RF power measurements conducted with a 3.4-V supply voltage and a Band 9 WCDMA HSDPA modulated signal are as follows. The SWPA delivers a P_out of 28.5 dBm, a power gain (G_p) of 28 dB, and a PAE of 39% while restricting the ACLR1 to less than -40 dBc in the main amplifier chain. In the sub-amplifier chain, 17 dBm of P_out, 23.5 dB of G_p, and 27% of PAE are obtained at the same ACLR1 level.

We investigate a finite-sized self-complementary bow-tie antenna (SC-BTA) integrated with a semiconductor mesa with respect to radiation characteristics such as the peak radiation frequency and bandwidth around the fundamental radiation mode. For this investigation, we utilize an equivalent circuit model of the SC-BTA derived in our previous work and a finite element method solver. Moreover, we derive design guidelines for the radiation characteristics in the form of size scaling-rules with respect to the antenna outer size for a terahertz transmitter.

In the newly finalized video coding standard, namely high efficiency video coding (HEVC), new notations like coding unit (CU), prediction unit (PU) and transformation unit (TU) are introduced to improve the coding performance. As a result, the reconstruction loop in intra encoding is heavily burdened to choose the best partitions or modes for them. In order to solve the bottleneck problems in cycle and hardware cost, this paper proposed a high-throughput and compact implementation for such a reconstruction loop. By “high-throughput”, it refers to that it has a fixed throughput of 32 pixel/cycle independent of the TU/PU size (except for 4×4 TUs). By “compact”, it refers to that it fully explores the reusability between discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) as well as that between quantization (Q) and de-quantization (IQ). Besides the contributions made in designing related hardware, this paper also provides a universal formula to analyze the cycle cost of the reconstruction loop and proposed a parallel-process scheme to further reduce the cycle cost. This design is verified on the Stratix IV FPGA. The basic structure achieved a maximum frequency of 150MHz and a hardware cost of 64K ALUTs, which could support the real time TU/PU partition decision for 4K×2K@20fps videos.