A High-Throughput and Compact Hardware Implementation for the Reconstruction Loop in HEVC Intra Encoding

Yibo FAN; Leilei HUANG; Zheng XIE; Xiaoyang ZENG

doi:10.1587/transele.E100.C.643

A High-Throughput and Compact Hardware Implementation for the Reconstruction Loop in HEVC Intra Encoding

Yibo FAN, Leilei HUANG, Zheng XIE, Xiaoyang ZENG

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In the newly finalized video coding standard, namely high efficiency video coding (HEVC), new notations like coding unit (CU), prediction unit (PU) and transformation unit (TU) are introduced to improve the coding performance. As a result, the reconstruction loop in intra encoding is heavily burdened to choose the best partitions or modes for them. In order to solve the bottleneck problems in cycle and hardware cost, this paper proposed a high-throughput and compact implementation for such a reconstruction loop. By “high-throughput”, it refers to that it has a fixed throughput of 32 pixel/cycle independent of the TU/PU size (except for 4×4 TUs). By “compact”, it refers to that it fully explores the reusability between discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) as well as that between quantization (Q) and de-quantization (IQ). Besides the contributions made in designing related hardware, this paper also provides a universal formula to analyze the cycle cost of the reconstruction loop and proposed a parallel-process scheme to further reduce the cycle cost. This design is verified on the Stratix IV FPGA. The basic structure achieved a maximum frequency of 150MHz and a hardware cost of 64K ALUTs, which could support the real time TU/PU partition decision for 4K×2K@20fps videos.

Publication: IEICE TRANSACTIONS on Electronics Vol.E100-C No.6 pp.643-654

Publication Date: 2017/06/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E100.C.643

Type of Manuscript: PAPER

Category: Integrated Electronics

Authors

Yibo FAN
  Fudan University
Leilei HUANG
  Fudan University
Zheng XIE
  Fudan University
Xiaoyang ZENG
  Fudan University

Keyword

reconstruction loop, discrete cosine transform (DCT), inverse discrete cosine transform (IDCT), quantization (Q), de-quantization (IQ), high efficiency video coding (HEVC)

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Yibo FAN, Leilei HUANG, Zheng XIE, Xiaoyang ZENG, "A High-Throughput and Compact Hardware Implementation for the Reconstruction Loop in HEVC Intra Encoding" in IEICE TRANSACTIONS on Electronics, vol. E100-C, no. 6, pp. 643-654, June 2017, doi: 10.1587/transele.E100.C.643.
Abstract: In the newly finalized video coding standard, namely high efficiency video coding (HEVC), new notations like coding unit (CU), prediction unit (PU) and transformation unit (TU) are introduced to improve the coding performance. As a result, the reconstruction loop in intra encoding is heavily burdened to choose the best partitions or modes for them. In order to solve the bottleneck problems in cycle and hardware cost, this paper proposed a high-throughput and compact implementation for such a reconstruction loop. By “high-throughput”, it refers to that it has a fixed throughput of 32 pixel/cycle independent of the TU/PU size (except for 4×4 TUs). By “compact”, it refers to that it fully explores the reusability between discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) as well as that between quantization (Q) and de-quantization (IQ). Besides the contributions made in designing related hardware, this paper also provides a universal formula to analyze the cycle cost of the reconstruction loop and proposed a parallel-process scheme to further reduce the cycle cost. This design is verified on the Stratix IV FPGA. The basic structure achieved a maximum frequency of 150MHz and a hardware cost of 64K ALUTs, which could support the real time TU/PU partition decision for 4K×2K@20fps videos.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E100.C.643/_p

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@ARTICLE{e100-c_6_643,
author={Yibo FAN, Leilei HUANG, Zheng XIE, Xiaoyang ZENG, },
journal={IEICE TRANSACTIONS on Electronics},
title={A High-Throughput and Compact Hardware Implementation for the Reconstruction Loop in HEVC Intra Encoding},
year={2017},
volume={E100-C},
number={6},
pages={643-654},
abstract={In the newly finalized video coding standard, namely high efficiency video coding (HEVC), new notations like coding unit (CU), prediction unit (PU) and transformation unit (TU) are introduced to improve the coding performance. As a result, the reconstruction loop in intra encoding is heavily burdened to choose the best partitions or modes for them. In order to solve the bottleneck problems in cycle and hardware cost, this paper proposed a high-throughput and compact implementation for such a reconstruction loop. By “high-throughput”, it refers to that it has a fixed throughput of 32 pixel/cycle independent of the TU/PU size (except for 4×4 TUs). By “compact”, it refers to that it fully explores the reusability between discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) as well as that between quantization (Q) and de-quantization (IQ). Besides the contributions made in designing related hardware, this paper also provides a universal formula to analyze the cycle cost of the reconstruction loop and proposed a parallel-process scheme to further reduce the cycle cost. This design is verified on the Stratix IV FPGA. The basic structure achieved a maximum frequency of 150MHz and a hardware cost of 64K ALUTs, which could support the real time TU/PU partition decision for 4K×2K@20fps videos.},
keywords={},
doi={10.1587/transele.E100.C.643},
ISSN={1745-1353},
month={June},}

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TY - JOUR
TI - A High-Throughput and Compact Hardware Implementation for the Reconstruction Loop in HEVC Intra Encoding
T2 - IEICE TRANSACTIONS on Electronics
SP - 643
EP - 654
AU - Yibo FAN
AU - Leilei HUANG
AU - Zheng XIE
AU - Xiaoyang ZENG
PY - 2017
DO - 10.1587/transele.E100.C.643
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E100-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2017
AB - In the newly finalized video coding standard, namely high efficiency video coding (HEVC), new notations like coding unit (CU), prediction unit (PU) and transformation unit (TU) are introduced to improve the coding performance. As a result, the reconstruction loop in intra encoding is heavily burdened to choose the best partitions or modes for them. In order to solve the bottleneck problems in cycle and hardware cost, this paper proposed a high-throughput and compact implementation for such a reconstruction loop. By “high-throughput”, it refers to that it has a fixed throughput of 32 pixel/cycle independent of the TU/PU size (except for 4×4 TUs). By “compact”, it refers to that it fully explores the reusability between discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) as well as that between quantization (Q) and de-quantization (IQ). Besides the contributions made in designing related hardware, this paper also provides a universal formula to analyze the cycle cost of the reconstruction loop and proposed a parallel-process scheme to further reduce the cycle cost. This design is verified on the Stratix IV FPGA. The basic structure achieved a maximum frequency of 150MHz and a hardware cost of 64K ALUTs, which could support the real time TU/PU partition decision for 4K×2K@20fps videos.
ER -