We propose a statistical processing method to reduce the time of chip test of high-resolution and low-speed analog-to-digital converters (ADCs). For this kinds of ADCs, due to the influence of noise, conventional histogram or momentum method suffers from long time to collect required data for averaging. The proposed method, based on physically weighing the ADC, intending to physical weights in ADC/DAC under test. It can suppress white noise to 1/22 than conventional method in a case of 10bit binary ADC. Or it can reduce test data to 1/8 or less, which directly means to reduce measuring time to 1/8 or less. In addition, it earns complete Integrated Non-Linearity (INL) and Differential Non-linearity (DNL) even missing codes happens due to less data points. In this report, we theoretically describe how to guarantee missing codes at lacked measured data points.

In this paper an analog-digital signal processing scheme for multichannel signal reception with low-IF receivers is proposed and its performance is investigated. In the low-IF receivers, the signal in the mirror frequency causes interference to the desired signal. In the proposed analog-digital signal processing scheme, the interference signal is extracted with the analog filter and the interference to the desired signal is reconstructed by LMS algorithm.

In this paper, we describe our SFQ circuit design and measurement carried out in SRL-ISTEC. We are studying an oversampling sigma-delta modulator and a counter-type decimation filter with multistage structure for developing AD converters for software-defined radio application. We are also developing a superconducting memory, whose peripheral circuits are constructed with SFQ circuits.

Optimization procedure on higher order Delta-sigma (ΔΣ) modulator coefficients is proposed. The procedure is based on the higher order ΔΣ modulator stability judgement method. The application specification can be satisfied with the proposed method. The 4th order modulator examples are illustrated. Optimized coefficients and its behavior model simulation results demonstrated that this methodology is suitable for the design of higher order ΔΣ AD converter. The coefficients tolerance up to 2% is allowed for switched-capacitor implementation, with not more than 3.5 dB SNR (Signal to Noise Ratio) degradation. The optimized coefficients improves 2 to 3 bit of the modulator's resolution than the previous proposed algorithm, and remains the stable input limit satisfies the original design requirement.

This paper reports the prehistory of software defined radio (SDR) studies in Japan. In 1999, a boom in the field of SDR started in Japan, and this year an ARIB study group completed its final report on SDR. SDR is a recently proposed technology concept and has attracted the attention of many communication engineering researchers. SDR will become one of the most important technologies in advanced communication, broadcasting and intelligent transportation systems on the 21st century. Although SDR has several attractive features, there are also many design issues to be solved. In this work we have examined these issues and discussed a new design methodology for wireless receivers in the SDR era.