We propose a statistical processing method to reduce the time of chip test of high-resolution and low-speed analog-to-digital converters (ADCs). For this kinds of ADCs, due to the influence of noise, conventional histogram or momentum method suffers from long time to collect required data for averaging. The proposed method, based on physically weighing the ADC, intending to physical weights in ADC/DAC under test. It can suppress white noise to 1/22 than conventional method in a case of 10bit binary ADC. Or it can reduce test data to 1/8 or less, which directly means to reduce measuring time to 1/8 or less. In addition, it earns complete Integrated Non-Linearity (INL) and Differential Non-linearity (DNL) even missing codes happens due to less data points. In this report, we theoretically describe how to guarantee missing codes at lacked measured data points.