A 0.027-mm2 Self-Calibrating Successive Approximation ADC Core in 0.18-µm CMOS
Summary :
We present a 10-bit 1-MS/s successive approximation analog-to-digital converter core including a charge redistribution digital-to-analog converter and a comparator. A new linearity calibration technique enables use of a nearly minimum capacitor limited by kT/C noise. The ADC core without digital control blocks has been fabricated in a 0.18-µm CMOS process and consumes 118 µW at 1.8 V power supply. Also, the active area of ADC core is realized to be 0.027 mm2. The calibration improves the SNDR by 13.4 dB and the SFDR by 21.0 dB. The measured SNDR and SFDR at 1 kHz input are 55.2 dB and 73.2 dB respectively.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E92-A No.2 pp.360-366
- Publication Date
- 2009/02/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E92.A.360
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
- Category
Authors
Keyword
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Yasuhide KURAMOCHI, Akira MATSUZAWA, Masayuki KAWABATA, "A 0.027-mm2 Self-Calibrating Successive Approximation ADC Core in 0.18-µm CMOS" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 2, pp. 360-366, February 2009, doi: 10.1587/transfun.E92.A.360.
Abstract: We present a 10-bit 1-MS/s successive approximation analog-to-digital converter core including a charge redistribution digital-to-analog converter and a comparator. A new linearity calibration technique enables use of a nearly minimum capacitor limited by kT/C noise. The ADC core without digital control blocks has been fabricated in a 0.18-µm CMOS process and consumes 118 µW at 1.8 V power supply. Also, the active area of ADC core is realized to be 0.027 mm2. The calibration improves the SNDR by 13.4 dB and the SFDR by 21.0 dB. The measured SNDR and SFDR at 1 kHz input are 55.2 dB and 73.2 dB respectively.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.360/_p
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@ARTICLE{e92-a_2_360,
author={Yasuhide KURAMOCHI, Akira MATSUZAWA, Masayuki KAWABATA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 0.027-mm2 Self-Calibrating Successive Approximation ADC Core in 0.18-µm CMOS},
year={2009},
volume={E92-A},
number={2},
pages={360-366},
abstract={We present a 10-bit 1-MS/s successive approximation analog-to-digital converter core including a charge redistribution digital-to-analog converter and a comparator. A new linearity calibration technique enables use of a nearly minimum capacitor limited by kT/C noise. The ADC core without digital control blocks has been fabricated in a 0.18-µm CMOS process and consumes 118 µW at 1.8 V power supply. Also, the active area of ADC core is realized to be 0.027 mm2. The calibration improves the SNDR by 13.4 dB and the SFDR by 21.0 dB. The measured SNDR and SFDR at 1 kHz input are 55.2 dB and 73.2 dB respectively.},
keywords={},
doi={10.1587/transfun.E92.A.360},
ISSN={1745-1337},
month={February},}
Copy
TY - JOUR
TI - A 0.027-mm2 Self-Calibrating Successive Approximation ADC Core in 0.18-µm CMOS
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 360
EP - 366
AU - Yasuhide KURAMOCHI
AU - Akira MATSUZAWA
AU - Masayuki KAWABATA
PY - 2009
DO - 10.1587/transfun.E92.A.360
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2009
AB - We present a 10-bit 1-MS/s successive approximation analog-to-digital converter core including a charge redistribution digital-to-analog converter and a comparator. A new linearity calibration technique enables use of a nearly minimum capacitor limited by kT/C noise. The ADC core without digital control blocks has been fabricated in a 0.18-µm CMOS process and consumes 118 µW at 1.8 V power supply. Also, the active area of ADC core is realized to be 0.027 mm2. The calibration improves the SNDR by 13.4 dB and the SFDR by 21.0 dB. The measured SNDR and SFDR at 1 kHz input are 55.2 dB and 73.2 dB respectively.
ER -
English
