This paper presents a resilient cache memory for dynamic variation tolerance in a 40-nm CMOS. The cache can perform sustained operations under a large-amplitude voltage droop. To realize sustained operation, the resilient cache exploits 7T/14T bit-enhancing SRAM and on-chip voltage/temperature monitoring circuit. 7T/14T bit-enhancing SRAM can reconfigure itself dynamically to a reliable bit-enhancing mode. The on-chip voltage/temperature monitoring circuit can sense a precise supply voltage level of a power rail of the cache. The proposed cache can dynamically change its operation mode using the voltage/temperature monitoring result and can operate reliably under a large-amplitude voltage droop. Experimental result shows that it does not fail with 25% and 30% droop of Vdd and it provides 91 times better failure rate with a 35% droop of Vdd compared with the conventional design.

We present a high performance AlGaAs/GaAs power HBT with very low thermal resistance for digital cellular phones. Device structure with emitter air-bridge is utilized and device layout is optimized to reduce thermal resistance based on three-dimensional thermal flow analysis, and in spite of a rather thick substrate (100 µm), which achieved a low thermal resistance of 23/W for a multi-finger (440 µm240 fingers) HBT. This 40 finger HBT achieved power added efficiency (PAE) of over 53%, 29.1 dBm output power (Pout) and high associated gain (Ga) of 13.5 dB with 50 kHz adjacent channel leakage power (Padj) of less than -48 dBc under a 948 MHz π/4-shifted QPSK modulation with 3.4 V emitter-collector voltage. We also investigated the difference of RF performance between two bias modes (constant base voltage and current), and found which mode is adequate for each stage in several stage power amplifier for the first time.