Well designed redundant via-aware standard cells (SCs) can increase the redundant via1 insertion rate in cell-based designs. However, in conventional methods, manual- and visual-based checks are required to locate pins and tune the geometries of layouts. These tasks can be very time consuming and unreliable. In this work, an O(Nlog N) redundant via-aware standard cell optimization scheme is developed. The proposed method is an efficient layout check and optimization scheme that considers various redundant via configurations including the double-via and rectangle-via to shorten the design time for standard cells. The optimized SCs effectively increase the redundant via insertion rate, and in particular the insertion rate of via1 for both concurrent routing and post-layout optimization. Furthermore, an automatic layout checker and optimizer are more efficient in identifying expandable metal 1 pins in libraries that contain numerous cells than are conventional visual check and manual optimization. Therefore, the proposed scheme not only solves the problem of a low via1 insertion rate in nanometer regimes, but also provides an efficient layout optimizer for designing standard cells. Experimental results indicate that the optimized standard cells increase the double-via1 insertion rates by 21.9%.