Rule-Based Redundant Via-Aware Standard Cell Design Considering Multiple Via Configuration
Summary :
Well designed redundant via-aware standard cells (SCs) can increase the redundant via1 insertion rate in cell-based designs. However, in conventional methods, manual- and visual-based checks are required to locate pins and tune the geometries of layouts. These tasks can be very time consuming and unreliable. In this work, an O(Nlog N) redundant via-aware standard cell optimization scheme is developed. The proposed method is an efficient layout check and optimization scheme that considers various redundant via configurations including the double-via and rectangle-via to shorten the design time for standard cells. The optimized SCs effectively increase the redundant via insertion rate, and in particular the insertion rate of via1 for both concurrent routing and post-layout optimization. Furthermore, an automatic layout checker and optimizer are more efficient in identifying expandable metal 1 pins in libraries that contain numerous cells than are conventional visual check and manual optimization. Therefore, the proposed scheme not only solves the problem of a low via1 insertion rate in nanometer regimes, but also provides an efficient layout optimizer for designing standard cells. Experimental results indicate that the optimized standard cells increase the double-via1 insertion rates by 21.9%.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E97-A No.2 pp.597-605
- Publication Date
- 2014/02/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E97.A.597
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
Authors
Tsang-Chi KAN
National Taiwan University of Science and Technology
Ying-Jung CHEN
National Taiwan University of Science and Technology
Hung-Ming HONG
National Taiwan University of Science and Technology
Shanq-Jang RUAN
National Taiwan University of Science and Technology
Keyword
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Tsang-Chi KAN, Ying-Jung CHEN, Hung-Ming HONG, Shanq-Jang RUAN, "Rule-Based Redundant Via-Aware Standard Cell Design Considering Multiple Via Configuration" in IEICE TRANSACTIONS on Fundamentals,
vol. E97-A, no. 2, pp. 597-605, February 2014, doi: 10.1587/transfun.E97.A.597.
Abstract: Well designed redundant via-aware standard cells (SCs) can increase the redundant via1 insertion rate in cell-based designs. However, in conventional methods, manual- and visual-based checks are required to locate pins and tune the geometries of layouts. These tasks can be very time consuming and unreliable. In this work, an O(Nlog N) redundant via-aware standard cell optimization scheme is developed. The proposed method is an efficient layout check and optimization scheme that considers various redundant via configurations including the double-via and rectangle-via to shorten the design time for standard cells. The optimized SCs effectively increase the redundant via insertion rate, and in particular the insertion rate of via1 for both concurrent routing and post-layout optimization. Furthermore, an automatic layout checker and optimizer are more efficient in identifying expandable metal 1 pins in libraries that contain numerous cells than are conventional visual check and manual optimization. Therefore, the proposed scheme not only solves the problem of a low via1 insertion rate in nanometer regimes, but also provides an efficient layout optimizer for designing standard cells. Experimental results indicate that the optimized standard cells increase the double-via1 insertion rates by 21.9%.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E97.A.597/_p
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@ARTICLE{e97-a_2_597,
author={Tsang-Chi KAN, Ying-Jung CHEN, Hung-Ming HONG, Shanq-Jang RUAN, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Rule-Based Redundant Via-Aware Standard Cell Design Considering Multiple Via Configuration},
year={2014},
volume={E97-A},
number={2},
pages={597-605},
abstract={Well designed redundant via-aware standard cells (SCs) can increase the redundant via1 insertion rate in cell-based designs. However, in conventional methods, manual- and visual-based checks are required to locate pins and tune the geometries of layouts. These tasks can be very time consuming and unreliable. In this work, an O(Nlog N) redundant via-aware standard cell optimization scheme is developed. The proposed method is an efficient layout check and optimization scheme that considers various redundant via configurations including the double-via and rectangle-via to shorten the design time for standard cells. The optimized SCs effectively increase the redundant via insertion rate, and in particular the insertion rate of via1 for both concurrent routing and post-layout optimization. Furthermore, an automatic layout checker and optimizer are more efficient in identifying expandable metal 1 pins in libraries that contain numerous cells than are conventional visual check and manual optimization. Therefore, the proposed scheme not only solves the problem of a low via1 insertion rate in nanometer regimes, but also provides an efficient layout optimizer for designing standard cells. Experimental results indicate that the optimized standard cells increase the double-via1 insertion rates by 21.9%.},
keywords={},
doi={10.1587/transfun.E97.A.597},
ISSN={1745-1337},
month={February},}
Copy
TY - JOUR
TI - Rule-Based Redundant Via-Aware Standard Cell Design Considering Multiple Via Configuration
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 597
EP - 605
AU - Tsang-Chi KAN
AU - Ying-Jung CHEN
AU - Hung-Ming HONG
AU - Shanq-Jang RUAN
PY - 2014
DO - 10.1587/transfun.E97.A.597
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E97-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2014
AB - Well designed redundant via-aware standard cells (SCs) can increase the redundant via1 insertion rate in cell-based designs. However, in conventional methods, manual- and visual-based checks are required to locate pins and tune the geometries of layouts. These tasks can be very time consuming and unreliable. In this work, an O(Nlog N) redundant via-aware standard cell optimization scheme is developed. The proposed method is an efficient layout check and optimization scheme that considers various redundant via configurations including the double-via and rectangle-via to shorten the design time for standard cells. The optimized SCs effectively increase the redundant via insertion rate, and in particular the insertion rate of via1 for both concurrent routing and post-layout optimization. Furthermore, an automatic layout checker and optimizer are more efficient in identifying expandable metal 1 pins in libraries that contain numerous cells than are conventional visual check and manual optimization. Therefore, the proposed scheme not only solves the problem of a low via1 insertion rate in nanometer regimes, but also provides an efficient layout optimizer for designing standard cells. Experimental results indicate that the optimized standard cells increase the double-via1 insertion rates by 21.9%.
ER -
English
