Recently, many AI-aided layout design systems are developed to reduce tedious manual intervention based on deep learning. However, most methods focus on a specific generation task. This paper explores a challenging problem to obtain multiple layout design generation (LDG), which generates floor plan or urban plan from a boundary input under a unified framework. One of the main challenges of multiple LDG is to obtain reasonable topological structures of layout generation with irregular boundaries and layout elements for different types of design. This paper formulates the multiple LDG task as an image-to-image translation problem, and proposes a conditional generative adversarial network (GAN), called LDGAN, with adaptive modules. The framework of LDGAN is based on a generator-discriminator architecture, where the generator is integrated with conditional convolution constrained by the boundary input and the attention module with channel and spatial features. Qualitative and quantitative experiments were conducted on the SCUT-AutoALP and RPLAN datasets, and the comparison with the state-of-the-art methods illustrate the effectiveness and superiority of the proposed LDGAN.

Fully homomorphic encryption (FHE) enables secret computations. Users can perform computation using data encrypted with FHE without decryption. Uploading private data without encryption to a public cloud has the risk of data leakage, which makes many users hesitant to utilize a public cloud. Uploading data encrypted with FHE avoids this risk, while still providing the computing power of the public cloud. In many cases, data are stored in HDDs because the data size increases significantly when FHE is used. One important data analysis is Apriori data mining. In this application, two files are accessed alternately, and this causes long-distance seeking on its HDD and low performance. In this paper, we propose a new striping layout with reservations for write areas. This method intentionally fragments files and arranges blocks to reduce the distance between blocks in a file and another file. It reserves the area for intermediate files of FHE Apriori. The performance of the proposed method was evaluated based on the I/O processing of a large FHE Apriori, and the results showed that the proposed method could improve performance by up to approximately 28%.

Graph layout is a critical component in graph visualization. This paper proposes GRAPHULY, a graph u-nets-based neural network, for end-to-end graph layout generation. GRAPHULY learns the multi-level graph layout process and can generate graph layouts without iterative calculation. We also propose to use Laplacian positional encoding and a multi-level loss fusion strategy to improve the layout learning. We evaluate the model with a random dataset and a graph drawing dataset and showcase the effectiveness and efficiency of GRAPHULY in graph visualization.

Graph layouts reveal global or local structures of graph data. However, there are few studies on assisting readers in better reconstructing a graph from a layout. This paper attempts to generate a layout whose edges can be reestablished. We reformulate the graph layout problem as an edge classification problem. The inputs are the vertex pairs, and the outputs are the edge existences. The trainable parameters are the laid-out coordinates of the vertices. We propose a binary classification-based graph layout (BCGL) framework in this paper. This layout aims to preserve the local structure of the graph and does not require the total similarity relationships of the vertices. We implement two concrete algorithms under the BCGL framework, evaluate our approach on a wide variety of datasets, and draw comparisons with several other methods. The evaluations verify the ability of the BCGL in local neighborhood preservation and its visual quality with some classic metrics.

We propose an augmented-reality-based method for arranging furniture using natural markers extracted from the edges of the walls of rooms. The proposed method extracts natural markers and estimates the camera parameters from single images of rooms using deep neural networks. Experimental results show that in all the measurements, the superimposition error of the proposed method was lower than that of general marker-based methods that use practical-sized markers.

With the commercialization of 5G mobile phones, Android drivers are increasing rapidly to utilize a large quantity of newly emerging feature-rich hardware. Most of these drivers are developed by third-party vendors and lack proper vulnerabilities review, posing a number of new potential risks to security and privacy. However, the complexity and diversity of Android drivers make the traditional analysis methods inefficient. For example, the driver-specific argument formats make traditional syscall fuzzers difficult to generate valid inputs, the pointer-heavy code makes static analysis results incomplete, and pointer casting hides the actual type. Triggering code deep in Android drivers remains challenging. We present CoLaFUZE, a coverage-guided and layout-aware fuzzing tool for automatically generating valid inputs and exploring the driver code. CoLaFUZE employs a kernel module to capture the data copy operation and redirect it to the fuzzing engine, ensuring that the correct size of the required data is transferred to the driver. CoLaFUZE leverages dynamic analysis and symbolic execution to recover the driver interfaces and generates valid inputs for the interfaces. Furthermore, the seed mutation module of CoLaFUZE leverages coverage information to achieve better seed quality and expose bugs deep in the driver. We evaluate CoLaFUZE on 5 modern Android mobile phones from the top vendors, including Google, Xiaomi, Samsung, Sony, and Huawei. The results show that CoLaFUZE can explore more code coverage compared with the state-of-the-art fuzzer, and CoLaFUZE successfully found 11 vulnerabilities in the testing devices.

We present a retrieval method for 3D CAD assemblies consisted of multiple components. The proposed method distinguishes not only shapes of 3D CAD assemblies but also layouts of their components. Similarity between two assemblies is computed from feature quantities of the components constituting the assemblies. In order to make the similarity robust to translation and rotation of an assembly in 3D space, we use the 3D Radon transform and the spherical harmonic transform. We show that this method has better retrieval precision and efficiency than targets for comparison by experimental evaluation.

One goal in stack-queue mixed layouts of a graph subdivision is to obtain a layout with minimum number of subdivision vertices per edge when the number of stacks and queues are given. Dujmović and Wood showed that for every integer s, q>0, every graph G has an s-stack q-queue subdivision layout with 4⌈log(s+q)q sn(G)⌉ (resp. 2+4⌈log(s+q)q qn(G)⌉) division vertices per edge, where sn(G) (resp. qn(G)) is the stack number (resp. queue number) of G. This paper improves these results by showing that for every integer s, q>0, every graph G has an s-stack q-queue subdivision layout with at most 2⌈logs+q-1sn(G)⌉ (resp. at most 2⌈logs+q-1qn(G)⌉ +4) division vertices per edge. That is, this paper improves previous results more, for graphs with larger stack number sn(G) or queue number qn(G) than given integers s and q. Also, the larger the given integer s is, the more this paper improves previous results.

In integrated circuit design of advanced technology nodes, layout density uniformity significantly influences the manufacturability due to the CMP variability. In analog design, especially, designers are suffering from passing the density checking since there are few useful tools. To tackle this issue, we focus a transistor-array(TA)-style analog layout, and propose a density optimization algorithm consistent with complicated design rules. Based on TA-style, we introduce a density-aware layout format to explicitly control the layout pattern density, and provide the mathematical optimization approach. Hence, a design flow incorporating our density optimization can drastically reduce the design time with fewer iterations. In a design case of an OPAMP layout in a 65nm CMOS process, the result demonstrates that the proposed approach achieves more than 48× speed-up compared with conventional manual layout, meanwhile it shows a good circuit performance in the post-layout simulation.

A topological quantum circuit is a representation model for topological quantum computation, which attracts much attention recently as a promising fault-tolerant quantum computation model by using 3D cluster states. A topological quantum circuit can be considered as a set of “loops,” and we can transform the topology of loops without changing the functionality of the circuit if the transformation satisfies certain conditions. Thus, there have been proposed many researches to optimize topological quantum circuits by transforming the topology. There are two directions of research to optimize topological quantum circuits. The first group of research considers so-called a placement and wiring problem where we consider how to place “parts” in a 3D space which corresponds to already optimized sub-circuits. The second group of research focuses on how to optimize the structure and locations of loops in a relatively small circuit which is treated as one part in the above-mentioned first group of research. This paper proposes a new idea for the second group of research; our idea is to consider topological transformations as a placement and wiring problem for modules which we derive from the information how loops are crossed. By using such a formulation, we can use the techniques for placement and wiring problems, and successfully obtain an optimized solution. We confirm by our experiment that our method indeed can reduce the cost much more than the method by Paetznick and Fowler.

We propose a method to find assembly models contained in another assembly model given as a query from a set of 3D CAD assembly models. A 3D CAD assembly model consists of multiple components and is constructed using a 3D CAD software. The proposed method distinguishes assembly models which consist of a subset of components constituting the query model and also whose components have the same layout as the subset of the components. We compute difference between the shapes and the layouts of the components from the sinograms which are constructed by the Radon transform of their projections from various angles. We evaluate the proposed method experimentally using the assembly models which we prepare as a benchmark. The proposed method can also be used to find the database models which contains a query model.

Because mobile users demand a high quality and energy-friendly video delivery service that efficiently uses wireless resources, we introduce an energy-efficient video delivery system by applying moving route navigation and playout buffer control based on the mobile throughput history data. The proposed system first determines the optimal travel route to achieve high-speed and energy-efficient communications. Then when a user enters a high throughput area, our system temporarily extends the video playout buffer size, and the user aggressively downloads video segments via a high-speed and energy-efficient wireless connection until the extended buffer is filled. After leaving this area, the user consumes video segments from the extended buffer in order to keep smooth video playback without wireless communications. We carry out computer simulations, laboratory and field experiments and confirm that the proposed system can achieve energy-efficient mobile video delivery.

In this work, the metal-oxide-metal (MOM) capacitor in the scaled CMOS process has been modeled at high frequencies using an EM simulator, and its layout has been optimized. The modeled parasitic resistance consists of four components, and the modeled parasitic inductance consists of the comb inductance and many mutual inductances. Each component of the parasitic resistance and inductance show different degrees of dependence on the finger length and on the number of fingers. The substrate network parameters also have optimum points. As such, the geometric dependence of the characteristics of the MOM capacitor is investigated and the optimum layout in the constant-capacitance case is proposed by calculating the results of the model. The proposed MOM capacitor structures for 50fF at f =60GHz are L =5μm with M =3, and, L =2μm with M =5 and that for 100fF at f =30GHz are L =9μm with M =3, and L =4μm with M =5. The target process is 65-nm CMOS.

Content extraction from deep Web pages has received great attention in recent years. However, the increasingly complicated HTML structure of Web documents makes it more difficult to recognize the data records by only analyzing the HTML source code. In this paper, we propose a method named LTDE to extract data records from a deep Web page. Instead of analyzing the HTML source code, LTDE utilizes the visual features of data records in deep Web pages. A Web page is considered as a finite set of visual blocks. The data records are the visual blocks that have similar layout. We also propose a pattern recognizing method named layout tree to cluster the similar layout visual blocks. The weight of all clusters is calculated, and the visual blocks in the cluster that has the highest weight are chosen as the data records to be extracted. The experiment results show that LTDE has higher effectiveness and better robustness for Web data extraction compared to previous works.

We propose a synthesis and automatic layout method for mixed-signal circuits with high regularity. As the first step of this research, a resistive digital-to-analog converter (RDAC) is presented. With a size calculation routine, the area of this RDAC is minimized while satisfying the required matching precision without any optimization loops. We propose to partition the design into slices comprising of both analog and digital cells. These cells are programmed to be synthesized as similar as custom P-Cells based on the calculation above, and automatically laid out to form one slice cell. To synthesize digital circuits, without using digital standard cell library, we propose a versatile unit digital block consisting of 8 transistors. With one or several blocks, the transistors' interconnections are programmed in the units to realize various logic gates. By using this block, the slice shapes are aligned so that the layout space in between the slices are minimized. The proposed mixed-signal slice-based partition facilitates the place-and-route of the whole RDAC. The post-layout simulation shows that the generated 9-bit RDAC achieves 1GHz sampling frequency, -0.11/0.09 and -0.30/0.75 DNL and INL, respectively, 3.57mW power consumption, and 0.0038mm2 active area.

This paper presents a layout-dependent manufacturability for analog integrated circuits. We focus on the relative variability of an input op-amp-pair used in an instrumentation amplifier (in-amp). We propose a subblock-level matching layout style such that subblocks of the op-amp-pair are superimposed aiming to suppress the relative variability dependent on the layout. We fabricate chips according to five superposed layout styles and evaluate the relative variability in terms of the DC-offset, so that we demonstrate the most effective layout style. Besides, we provide a manufacturability simulation methodology to evaluate the in-amp considering the relative variability of the op-amp-pair based on the measurement results. Comparing the simulation result and the performances of fabricated in-amps, we are convinced our methodology can evaluate the layout-dependency of the manufacturability by the simulation.

We describe a calculation tool and modeling methods to find self and mutual inductance and current distribution in superconductive multilayer circuit layouts. Accuracy of the numerical solver is discussed and compared with experimental measurements. Effects of modeling parameter selection on calculation results are shown, and we make conclusions on the selection of modeling parameters for fast but sufficiently accurate calculations when calibration methods are used. Circuit theory for the calculation of branch impedances from the output of the numerical solver is discussed, and compensation for solution difficulties is shown through example. We elaborate on the construction of extraction models for superconductive integrated circuits, with and without resistive branches. We also propose a method to calculate current distribution in a multilayer circuit with multiple bias current feed points. Finally, detailed examples are shown where the effects of stacked vias, bias pillars, coupling, ground connection stacks and ground return currents in circuit layouts for the AIST advanced process (ADP2) and standard process (STP2) are analyzed. We show that multilayer inductance and current distribution extraction in such circuits provides much more information than merely branch inductance, and can be used to improve layouts; for example through reduced coupling between conductors.

In this paper, we consider the stack layout of the bubble-sort graph. The bubble-sort graph is a type of Cayley graph on a symmetric group; the bubble-sort graph has an important role for the study of Cayley graphs as interconnection networks. The stack layout and the queue layout problem that are treated in this paper have been studied widely. In this paper, we show that the stack number of the bubble-sort graph BS(n) is either n-1 or n-2. In addition, we show that an upper bound of the queue number of BS(n) is n-2.

As semiconductor manufacturing processing scaling down, leakage current of CMOS circuits is becoming a dominant contributor to power dissipation. This paper provides an efficient leakage current reduction (LCR) technique for low-power and low-frequency circuit designs in terms of design rules and layout parameters related to layout dependent effects. We address the LCR technique both for analog and digital circuits, and present a design case when applying the LCR techniqe to a successive-approximation-register (SAR) analog-to-digital converter (ADC), which typically employs analog and digital transistors. In the post-layout simulation results by HSPICE, an SAR-ADC with the LCR technique achieves 38.6-nW as the total power consumption. Comparing with the design without the LCR technique, we attain about 30% total energy reduction.

Smartphones have become vital devices in the current on-the-go Thai culture. Typically, virtual keyboards serve as tools for text input on smartphones. Due to the limited screen area and the large number of Thai characters, the size of each button on the keyboard is quite small. This leads to character mistyping and low typing speed. In this paper, we present a typical framework of a Thai Input Method on smartphones which includes four processes; Character Candidate Generation, Word Candidate Generation, Word Candidate Display, and Model Update. This framework not only works with Thai, it works with other letter-based languages as well. We also review virtual keyboards and techniques currently used and available for Thai text input.