Compaction of Topological Quantum Circuits by Modularization

Kota ASAI; Shigeru YAMASHITA

doi:10.1587/transfun.E102.A.624

IEICE TRANSACTIONS on Fundamentals

Compaction of Topological Quantum Circuits by Modularization

Kota ASAI, Shigeru YAMASHITA

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A topological quantum circuit is a representation model for topological quantum computation, which attracts much attention recently as a promising fault-tolerant quantum computation model by using 3D cluster states. A topological quantum circuit can be considered as a set of “loops,” and we can transform the topology of loops without changing the functionality of the circuit if the transformation satisfies certain conditions. Thus, there have been proposed many researches to optimize topological quantum circuits by transforming the topology. There are two directions of research to optimize topological quantum circuits. The first group of research considers so-called a placement and wiring problem where we consider how to place “parts” in a 3D space which corresponds to already optimized sub-circuits. The second group of research focuses on how to optimize the structure and locations of loops in a relatively small circuit which is treated as one part in the above-mentioned first group of research. This paper proposes a new idea for the second group of research; our idea is to consider topological transformations as a placement and wiring problem for modules which we derive from the information how loops are crossed. By using such a formulation, we can use the techniques for placement and wiring problems, and successfully obtain an optimized solution. We confirm by our experiment that our method indeed can reduce the cost much more than the method by Paetznick and Fowler.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E102-A No.4 pp.624-632

Publication Date: 2019/04/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1587/transfun.E102.A.624

Type of Manuscript: PAPER

Category: VLSI Design Technology and CAD

Authors

Kota ASAI
Ritsumeikan University
Shigeru YAMASHITA
Ritsumeikan University

Keyword

topological quantum computation, qubit layout, circuit optimization, simulated annealing

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Kota ASAI, Shigeru YAMASHITA, "Compaction of Topological Quantum Circuits by Modularization" in IEICE TRANSACTIONS on Fundamentals, vol. E102-A, no. 4, pp. 624-632, April 2019, doi: 10.1587/transfun.E102.A.624.
Abstract: A topological quantum circuit is a representation model for topological quantum computation, which attracts much attention recently as a promising fault-tolerant quantum computation model by using 3D cluster states. A topological quantum circuit can be considered as a set of “loops,” and we can transform the topology of loops without changing the functionality of the circuit if the transformation satisfies certain conditions. Thus, there have been proposed many researches to optimize topological quantum circuits by transforming the topology. There are two directions of research to optimize topological quantum circuits. The first group of research considers so-called a placement and wiring problem where we consider how to place “parts” in a 3D space which corresponds to already optimized sub-circuits. The second group of research focuses on how to optimize the structure and locations of loops in a relatively small circuit which is treated as one part in the above-mentioned first group of research. This paper proposes a new idea for the second group of research; our idea is to consider topological transformations as a placement and wiring problem for modules which we derive from the information how loops are crossed. By using such a formulation, we can use the techniques for placement and wiring problems, and successfully obtain an optimized solution. We confirm by our experiment that our method indeed can reduce the cost much more than the method by Paetznick and Fowler.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E102.A.624/_p

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@ARTICLE{e102-a_4_624,
author={Kota ASAI, Shigeru YAMASHITA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Compaction of Topological Quantum Circuits by Modularization},
year={2019},
volume={E102-A},
number={4},
pages={624-632},
abstract={A topological quantum circuit is a representation model for topological quantum computation, which attracts much attention recently as a promising fault-tolerant quantum computation model by using 3D cluster states. A topological quantum circuit can be considered as a set of “loops,” and we can transform the topology of loops without changing the functionality of the circuit if the transformation satisfies certain conditions. Thus, there have been proposed many researches to optimize topological quantum circuits by transforming the topology. There are two directions of research to optimize topological quantum circuits. The first group of research considers so-called a placement and wiring problem where we consider how to place “parts” in a 3D space which corresponds to already optimized sub-circuits. The second group of research focuses on how to optimize the structure and locations of loops in a relatively small circuit which is treated as one part in the above-mentioned first group of research. This paper proposes a new idea for the second group of research; our idea is to consider topological transformations as a placement and wiring problem for modules which we derive from the information how loops are crossed. By using such a formulation, we can use the techniques for placement and wiring problems, and successfully obtain an optimized solution. We confirm by our experiment that our method indeed can reduce the cost much more than the method by Paetznick and Fowler.},
keywords={},
doi={10.1587/transfun.E102.A.624},
ISSN={1745-1337},
month={April},}

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TY - JOUR
TI - Compaction of Topological Quantum Circuits by Modularization
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 624
EP - 632
AU - Kota ASAI
AU - Shigeru YAMASHITA
PY - 2019
DO - 10.1587/transfun.E102.A.624
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E102-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2019
AB - A topological quantum circuit is a representation model for topological quantum computation, which attracts much attention recently as a promising fault-tolerant quantum computation model by using 3D cluster states. A topological quantum circuit can be considered as a set of “loops,” and we can transform the topology of loops without changing the functionality of the circuit if the transformation satisfies certain conditions. Thus, there have been proposed many researches to optimize topological quantum circuits by transforming the topology. There are two directions of research to optimize topological quantum circuits. The first group of research considers so-called a placement and wiring problem where we consider how to place “parts” in a 3D space which corresponds to already optimized sub-circuits. The second group of research focuses on how to optimize the structure and locations of loops in a relatively small circuit which is treated as one part in the above-mentioned first group of research. This paper proposes a new idea for the second group of research; our idea is to consider topological transformations as a placement and wiring problem for modules which we derive from the information how loops are crossed. By using such a formulation, we can use the techniques for placement and wiring problems, and successfully obtain an optimized solution. We confirm by our experiment that our method indeed can reduce the cost much more than the method by Paetznick and Fowler.
ER -

IEICE TRANSACTIONS on Fundamentals