IEICE TRANSACTIONS on Fundamentals
Modeling and Layout Optimization of MOM Capacitor for High-Frequency Applications
Summary :
In this work, the metal-oxide-metal (MOM) capacitor in the scaled CMOS process has been modeled at high frequencies using an EM simulator, and its layout has been optimized. The modeled parasitic resistance consists of four components, and the modeled parasitic inductance consists of the comb inductance and many mutual inductances. Each component of the parasitic resistance and inductance show different degrees of dependence on the finger length and on the number of fingers. The substrate network parameters also have optimum points. As such, the geometric dependence of the characteristics of the MOM capacitor is investigated and the optimum layout in the constant-capacitance case is proposed by calculating the results of the model. The proposed MOM capacitor structures for 50fF at f =60GHz are L =5μm with M =3, and, L =2μm with M =5 and that for 100fF at f =30GHz are L =9μm with M =3, and L =4μm with M =5. The target process is 65-nm CMOS.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E101-A No.2 pp.441-446
- Publication Date
- 2018/02/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E101.A.441
- Type of Manuscript
- Special Section LETTER (Special Section on Analog Circuit Techniques and Related Topics)
- Category
Authors
Yuka ITANO
Okayama Prefectural University
Taishi KITANO
Okayama Prefectural University
Yuta SAKAMOTO
Okayama Prefectural University
Kiyotaka KOMOKU
Okayama Prefectural University
Takayuki MORISHITA
Okayama Prefectural University
Nobuyuki ITOH
Okayama Prefectural University
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Yuka ITANO, Taishi KITANO, Yuta SAKAMOTO, Kiyotaka KOMOKU, Takayuki MORISHITA, Nobuyuki ITOH, "Modeling and Layout Optimization of MOM Capacitor for High-Frequency Applications" in IEICE TRANSACTIONS on Fundamentals,
vol. E101-A, no. 2, pp. 441-446, February 2018, doi: 10.1587/transfun.E101.A.441.
Abstract: In this work, the metal-oxide-metal (MOM) capacitor in the scaled CMOS process has been modeled at high frequencies using an EM simulator, and its layout has been optimized. The modeled parasitic resistance consists of four components, and the modeled parasitic inductance consists of the comb inductance and many mutual inductances. Each component of the parasitic resistance and inductance show different degrees of dependence on the finger length and on the number of fingers. The substrate network parameters also have optimum points. As such, the geometric dependence of the characteristics of the MOM capacitor is investigated and the optimum layout in the constant-capacitance case is proposed by calculating the results of the model. The proposed MOM capacitor structures for 50fF at f =60GHz are L =5μm with M =3, and, L =2μm with M =5 and that for 100fF at f =30GHz are L =9μm with M =3, and L =4μm with M =5. The target process is 65-nm CMOS.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E101.A.441/_p
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@ARTICLE{e101-a_2_441,
author={Yuka ITANO, Taishi KITANO, Yuta SAKAMOTO, Kiyotaka KOMOKU, Takayuki MORISHITA, Nobuyuki ITOH, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Modeling and Layout Optimization of MOM Capacitor for High-Frequency Applications},
year={2018},
volume={E101-A},
number={2},
pages={441-446},
abstract={In this work, the metal-oxide-metal (MOM) capacitor in the scaled CMOS process has been modeled at high frequencies using an EM simulator, and its layout has been optimized. The modeled parasitic resistance consists of four components, and the modeled parasitic inductance consists of the comb inductance and many mutual inductances. Each component of the parasitic resistance and inductance show different degrees of dependence on the finger length and on the number of fingers. The substrate network parameters also have optimum points. As such, the geometric dependence of the characteristics of the MOM capacitor is investigated and the optimum layout in the constant-capacitance case is proposed by calculating the results of the model. The proposed MOM capacitor structures for 50fF at f =60GHz are L =5μm with M =3, and, L =2μm with M =5 and that for 100fF at f =30GHz are L =9μm with M =3, and L =4μm with M =5. The target process is 65-nm CMOS.},
keywords={},
doi={10.1587/transfun.E101.A.441},
ISSN={1745-1337},
month={February},}
Copy
TY - JOUR
TI - Modeling and Layout Optimization of MOM Capacitor for High-Frequency Applications
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 441
EP - 446
AU - Yuka ITANO
AU - Taishi KITANO
AU - Yuta SAKAMOTO
AU - Kiyotaka KOMOKU
AU - Takayuki MORISHITA
AU - Nobuyuki ITOH
PY - 2018
DO - 10.1587/transfun.E101.A.441
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E101-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2018
AB - In this work, the metal-oxide-metal (MOM) capacitor in the scaled CMOS process has been modeled at high frequencies using an EM simulator, and its layout has been optimized. The modeled parasitic resistance consists of four components, and the modeled parasitic inductance consists of the comb inductance and many mutual inductances. Each component of the parasitic resistance and inductance show different degrees of dependence on the finger length and on the number of fingers. The substrate network parameters also have optimum points. As such, the geometric dependence of the characteristics of the MOM capacitor is investigated and the optimum layout in the constant-capacitance case is proposed by calculating the results of the model. The proposed MOM capacitor structures for 50fF at f =60GHz are L =5μm with M =3, and, L =2μm with M =5 and that for 100fF at f =30GHz are L =9μm with M =3, and L =4μm with M =5. The target process is 65-nm CMOS.
ER -
English
