In video distribution services such as video streaming, the providers must satisfy the various quality demands of the users. One of the human-centric indexes used to assess video quality is the quality of experience (QoE). In video streaming, the video bitrate, video freezing time, and video bitrate switching are significant determiners of QoE. To provide high-quality video streaming services, adaptive streaming using the Moving Picture Experts Group dynamic adaptive streaming over Hypertext Transfer Protocol (MPEG-DASH) is widely utilized. One of the conventional bitrate selection methods for MPEG-DASH selects the bitrate such that the amount of buffered data in the playback buffer, i.e., the playback buffer level, can be maintained at a constant value. This method can avoid buffer overflow and video freezing based on feedback control; however, this method induces high-frequency video bitrate switching, which can degrade QoE. To overcome this issue, this paper proposes a bitrate selection method in an adaptive video steaming for MPEG-DASH to improve the QoE by minimizing the bitrate fluctuation. To this end, the proposed method does not change the bitrate if the playback buffer level is not around its upper or lower limit, corresponding to the full or empty state of the playback buffer, respectively. In particular, to avoid buffer overflow and video freezing, the proposed method selects the bitrate based on proportional-derivative (PD) control to maintain the playback buffer level at a target level, which corresponds to an upper or lower threshold of the playback buffer level. Simulations confirm that, the proposed method offers better QoE than the conventional method for users with various preferences.

In this work, the metal-oxide-metal (MOM) capacitor in the scaled CMOS process has been modeled at high frequencies using an EM simulator, and its layout has been optimized. The modeled parasitic resistance consists of four components, and the modeled parasitic inductance consists of the comb inductance and many mutual inductances. Each component of the parasitic resistance and inductance show different degrees of dependence on the finger length and on the number of fingers. The substrate network parameters also have optimum points. As such, the geometric dependence of the characteristics of the MOM capacitor is investigated and the optimum layout in the constant-capacitance case is proposed by calculating the results of the model. The proposed MOM capacitor structures for 50fF at f =60GHz are L =5μm with M =3, and, L =2μm with M =5 and that for 100fF at f =30GHz are L =9μm with M =3, and L =4μm with M =5. The target process is 65-nm CMOS.