1-4hit |
Yoshitaka NOZAKI Takashi WATANABE
Rehabilitation and evaluation of motor function are important for motor disabled patients. In stride length estimation using an IMU attached to the foot, it is necessary to detect the time of the movement state, in which acceleration should be integrated. In our previous study, acceleration thresholds were used to determine the integration section, so it was necessary to adjust the threshold values for each subject. The purpose of this study was to develop a method for estimating stride length automatically using an artificial neural network (ANN). In this paper, a 4-layer ANN with feature extraction layers trained by autoencoder was tested. In addition, the methods of searching for the local minimum of acceleration or ANN output after detecting the movement state section by ANN were examined. The proposed method estimated the stride length for healthy subjects with error of -1.88 ± 2.36%, which was almost the same as the previous threshold based method (-0.97 ± 2.68%). The correlation coefficients between the estimated stride length and the reference value were 0.981 and 0.976 for the proposed and previous methods, respectively. The error ranges excluding outliers were between -7.03% and 3.23%, between -7.13% and 5.09% for the proposed and previous methods, respectively. The proposed method would be effective because the error range was smaller than the conventional method and no threshold adjustment was required.
In this paper, an area-efficient decoder architecture is proposed for the quasi-cyclic low-density parity check (QC-LDPC) codes specified in the IEEE 802.16e WiMAX standard. The decoder supports all the code rates and codeword lengths defined in the standard. In order to achieve low area and maximize hardware utilization, the decoder utilizes 4 decoding function units, which is the greatest common divisor of the expansion factors. In addition, the decoder adopts a novel scheduling scheme named stride scheduling, which stores the extrinsic messages in non-sequential order to replace the conventional complex flexible permutation network with simple small-sized cyclic shifters and also minimize the number of memory accesses. To further minimize the complexity, the number of extrinsic memory instances for 24 block columns is reduced to 5 banks by identifying independent sets. All the memory instances used in the decoder are single-port memories which cost less area and price compared to dual-port ones. Finally, the decoding function units have partially parallel structure to make the decoding throughput sufficiently over the requirement of the WiMAX standard. The proposed decoder is synthesized with 49 K equivalent gates and 54,144 bits of memory, and the implementation occupies 0.40 mm2 in a 65 nm CMOS technology.
Young-Woong KO Ho-Min JUNG Wan-Yeon LEE Min-Ja KIM Chuck YOO
In this paper, we propose a stride static chunking deduplication algorithm using a hybrid approach that exploits the advantages of static chunking and byte-shift chunking algorithm. The key contribution of our approach is to reduce the computation time and enhance deduplication performance. We assume that duplicated data blocks are generally gathered into groups; thus, if we find one duplicated data block using byte-shift, then we can find subsequent data blocks with the static chunking approach. Experimental results show that stride static chunking algorithm gives significant benefits over static chunking, byte-shift chunking and variable-length chunking algorithm, particularly for reducing processing time and storage space.
Prefetching is a promising approach to tackle the memory latency problem. Two basic variants of hardware data prefetching methods are sequential prefetching and stride prefetching. The latter based on stride calculation of future references has the potential to out-perform the former which is based on the data locality. In this paper, a typical stride prefetching and its improved version, adaptive stride prefetching, are compared in quantitative way using simulation for some parallel benchmark programs in the context of uniform memory access and non-uniform memory access architectures. The simulation results show that adaptability of stride is essential since the proposed adaptive scheme can reduce pending stall time which is large in the typical scheme.