This work reports a novel power-rail electrostatic discharge (ESD) clamp circuit with parasitic bipolar-junction-transistor (BJT) and channel parallel shunt paths. The parallel shunt paths are formed by delivering a tiny ratio of drain voltage to the gate terminal of the clamp device in ESD events. Under such a mechanism, the proposed circuit achieves enhanced robustness over those of both gate-grounded NMOS (ggNMOS) and the referenced gate-coupled NMOS (gcNMOS). Besides, the proposed circuit also achieves improved fast power-up immunity over that of the referenced gcNMOS. All investigated designs are fabricated in a 65-nm CMOS process. Transmission-line-pulsing (TLP) and human-body-model (HBM) test results have both confirmed the performance enhancements of the proposed circuit. Finally, the validity of the achieved performance enhancements on other trigger circuits is essentially revealed in this work.

Layout strategies including source edge to substrate space (SESS) and inserted substrate-pick stripes of gate-grounded NMOS(ggNMOS) are optimized in this work for on-chip electrostatic discharge (ESD) protection. In order to fully investigate influences of substrate resistors on triggering and conduction behaviors of ggNMOS, various devices are designed and fabricated in a 65-nm CMOS process. Direct current (DC), transmission-line-pulsing (TLP), human body model (HBM) and very-fast TLP (VF-TLP) tests are executed to fully characterize performance of fabricated ggNMOS. Test results reveal that an enlarged SESS parameter results in an earlier triggering behavior of ggNMOS, which presents a layout option for subtle adjustable triggering behaviors. Besides, inserted substrate-pick stripes are proved to have a bell-shape influence on the ESD robustness of ggNMOS and this bell-shape influence is valid in TLP, HBM and VF-TLP tests. Moreover, the most ESD-robust ggNMOS optimized under different inserted substrate-pick stripes always achieves a higher HBM level over the traditional ggNMOS at each concerned total device-width. Physical mechanisms of test results will be deeply discussed in this work.